16-Channel, 16-Bit nanoDAC+ with 2 ppm/C Voltage Reference Temperature Coefficient, SPI Interface Data Sheet AD5679R FEATURES Table 1. Octal and 16-Channel nanoDAC+ Devices No. of High performance Channels Interface Reference 16-Bit 12-Bit High relative accuracy (INL): 4 LSB maximum at 16 bits 1 8 SPI Internal AD5676R AD5672R TUE: 0.14% of FSR maximum External AD5676 Not Offset error: 1.5 mV maximum applicable Gain error: 0.06% of FSR maximum 2 8 IC Internal AD5675R AD5671R Low drift 2.5 V voltage reference temperature coefficient: 16 SPI Internal AD5679R 2 ppm/C typical 40 mA short-circuit current 1 SPI = serial peripheral interface. Wide operating ranges 40C to +125C temperature range PRODUCT HIGHLIGHTS 2.7 V to 5.5 V power supply range 1. High channel density Simplified implementation 16 channels in 4 mm 4 mm LFCSP User selectable gain of 1 or 2 (GAIN pin) 2. High relative accuracy (integral nonlinearity (INL)) 1.8 V logic compatibility 4 LSB maximum 50 MHz SPI with readback or daisy chain 3. Low drift, 2.5 V, on-chip reference 28-lead, 4 mm 4 mm, RoHS compliant LFCSP APPLICATIONS Optical transceivers Base station power amplifiers Process control (programmable logic controller (PLC) input/output cards) Industrial automation Data acquisition systems FUNCTIONAL BLOCK DIAGRAM VLOGIC VDD VREF 2.5V REF AD5679R BUFFER INPUT DAC STRING VOUT0 REGISTER REGISTER DAC 0 BUFFER INPUT DAC STRING VOUT1 REGISTER REGISTER DAC 1 SCLK BUFFER INPUT DAC STRING VOUT2 REGISTER REGISTER DAC 2 SYNC BUFFER INPUT DAC STRING VOUT3 REGISTER REGISTER DAC 3 SDI BUFFER SDO INPUT DAC STRING VOUT14 REGISTER REGISTER DAC 14 BUFFER INPUT DAC STRING LDAC VOUT15 REGISTER REGISTER DAC 15 RESET POWER-ON GAIN POWER-DOWN RESET 1/2 LOGIC GAIN GND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 17326-001AD5679R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands .................................................. 22 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 22 Product Highlights ........................................................................... 1 Readback Operation .................................................................. 22 Functional Block Diagram .............................................................. 1 Power-Down Operation ............................................................ 23 Revision History ............................................................................... 2 LDAC Load DAC (Hardware Pin) ........................................... 24 General Description ......................................................................... 3 LDAC Mask Register ................................................................. 24 Specif icat ions ..................................................................................... 4 RESET Hardware Reset ( ) .......................................................... 25 AC Characteristics ........................................................................ 6 Power-On Reset Internal Circuit.............................................. 25 Timing Characteristics ................................................................ 6 Software Reset ............................................................................. 25 Daisy-Chain and Readback Timing Characteristics ............... 7 Internal Reference Setup ........................................................... 25 Absolute Maximum Ratings ............................................................ 9 Solder Heat Reflow ..................................................................... 25 Thermal Resistance ...................................................................... 9 Thermal Hysteresis .................................................................... 25 ESD Caution .................................................................................. 9 Applications Information .............................................................. 26 Pin Configuration and Function Descriptions ........................... 10 Power Supply Recommendations ............................................. 26 Typical Performance Characteristics ........................................... 11 Microprocessor Interfacing ....................................................... 26 Terminology .................................................................................... 18 AD5679R to ADSP-BF531 Interface ........................................ 26 Theory of Operation ...................................................................... 20 AD5679R to SPORT Interface .................................................. 26 DAC .............................................................................................. 20 Layout Guidelines....................................................................... 26 Transfer Function ....................................................................... 20 Galvanically Isolated Interface ................................................. 27 DAC Architecture ....................................................................... 20 Outline Dimensions ....................................................................... 28 Serial Interface ............................................................................ 20 Ordering Guide .......................................................................... 28 Standalone Operation ................................................................ 22 REVISION HISTORY 8/2019Revision 0: Initial Version Rev. 0 Page 2 of 28