Tiny 16-/14-/12-Bit SPI nanoDAC+, with
2 (16-Bit) LSB INL and 2 ppm/C Reference
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
FEATURES FUNCTIONAL BLOCK DIAGRAM
V * V V
LOGIC REF DD
Ultrasmall package: 2 mm 2 mm, 8-lead LFCSP
High relative accuracy (INL): 2 LSB maximum at 16 bits
POWER-ON AD5683R/
2.5V
AD5683R/AD5682R/AD5681R RESET
AD5682R/
LDAC REF
AD5681R
Low drift, 2.5 V reference: 2 ppm/C typical
REF
Selectable span output: 2.5 V or 5 V
DAC
OUTPUT
16-/14-/12-BIT V
REGISTER OUT
BUFFER
DAC
AD5683
RESET
External reference only
Selectable span output: V or 2 V
REF REF
INPUT POWER-DOWN
RESISTOR
CONTROL LOGIC CONTROL LOGIC
NETWORK
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: 1.5 mV maximum
*NOT AVAILABLE IN ALL THE MODELS
Gain error: 0.05% of FSR maximum
Low glitch: 0.1 nV-sec
SYNC SCLK SDI SDO* GND
High drive capability: 20 mA
Figure 1. AD5683R/AD5682R/AD5681R MSOP
Low power: 1.2 mW at 3.3 V (For more information, see the Functional Block DiagramsLFCSP section.)
Independent logic supply: 1.62 V logic compatible
Wide operating temperature range: 40C to +105C
Robust 4 kV HBM ESD protection
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
GENERAL DESCRIPTION
Table 1. Single-Channel nanoDAC+ Portfolio
The AD5683R/AD5682R/AD5681R/AD5683, members of the Interface Reference 16-Bit 14-Bit 12-Bit
nanoDAC+ family, are low power, single-channel, 16-/14-/12-bit
SPI Internal AD5683R AD5682R AD5681R
buffered voltage out digital-to-analog converters (DACs). The
External AD5683
2
devices, except the AD5683, include an enabled by default internal
I C Internal AD5693R AD5692R AD5691R
2.5 V reference, offering 2 ppm/C drift. The output span can be
External AD5693
programmed to be 0 V to V or 0 V to 2 V . All devices
REF REF
operate from a single 2.7 V to 5.5 V supply and are guaranteed PRODUCT HIGHLIGHTS
monotonic by design. The devices are available in a 2.00 mm
1. High Relative Accuracy (INL).
2.00 mm, 8-lead LFCSP or a 10-lead MSOP.
AD5683R/AD5683 (16-bit): 2 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
The internal power-on reset circuit ensures that the DAC register
2 ppm/C typical temperature coefficient.
is written to zero scale at power-up while the internal output
5 ppm/C maximum temperature coefficient.
buffer is configured in normal mode. The AD5683R/AD5682R
3. Two Package Options.
/AD5681R/AD5683 contain a power-down mode that reduces
2.00 mm 2.00 mm, 8-lead LFCSP.
the current consumption of the device to 2 A (maximum) at 5 V
10-lead MSOP.
and provides software selectable output loads while in power-
down mode.
The AD5683R/AD5682R/AD5681R/AD5683 use a versatile
3-wire serial interface that operates at clock rates of up to 50 MHz.
RESET
Some devices also include asynchronous pin and VLOGIC
pin options, allowing 1.8 V compatibility.
Rev. D Document Feedback
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11955-001AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Digital-to-Analog Converter .................................................... 19
Applications ....................................................................................... 1 Transfer Function ....................................................................... 19
Functional Block Diagram .............................................................. 1 DAC Architecture....................................................................... 19
General Description ......................................................................... 1 Serial Interface ................................................................................ 21
Product Highlights ........................................................................... 1 SPI Serial Data Interface ............................................................ 21
Revision History ............................................................................... 2 Short Write Operation (AD5681R Only) ................................ 21
Functional Block DiagramsLFCSP............................................. 3 Internal Registers ........................................................................ 23
Specifications ..................................................................................... 4 Commands .................................................................................. 23
AC Characteristics ........................................................................ 6 Hardware LDAC ......................................................................... 25
Timing Characteristics ................................................................ 6
Hardware RESET ........................................................................ 25
Absolute Maximum Ratings ............................................................ 8
Thermal Hysteresis .................................................................... 26
Thermal Resistance ...................................................................... 8
Power-Up Sequence ................................................................... 26
ESD Caution .................................................................................. 8
Recommended Regulator .......................................................... 26
Pin Configurations and Function Descriptions ........................... 9
Layout Guidelines....................................................................... 26
Typical Performance Characteristics ........................................... 11
Outline Dimensions ....................................................................... 27
Terminology .................................................................................... 17
Ordering Guide .......................................................................... 28
Theory of Operation ...................................................................... 19
REVISION HISTORY
12/2016Rev. C to Rev. D 10/2014Rev. A to Rev. B
Changed 1.8 V to 1.62 V, 1.8 V 10% to 1.62 V, 5 V + 10% to 5.5 V, Changes to Table 1 ............................................................................. 1
and 1.8 V VLOGIC 2.7 V to 1.62 V VLOGIC 2.7 V ..... Throughout Changes to Figure 14 ...................................................................... 11
Changes to DC Power Supply Rejection Ratio, PSRR, Test Added Recommended Regulator Section ................................... 26
Conditions/Comments Column, Table 2 ......................................... 4 Changes to Ordering Guide .......................................................... 28
3/2016Rev. B to Rev. C 1/2014Rev. 0 to Rev. A
Change to Features Section .............................................................. 1
Changes to Features Section............................................................ 1
Changes to Specifications Section .................................................. 4 Removed Endnote 2, Endnote 3, Endnote 5, and Endnote 6,
Changes to Table 2 ............................................................................ 5 Table 2; Renumbered Sequentially .................................................. 5
Changes to AC Characteristics Section, Timing Characteristics Removed Endnote 2, Table 3; Renumbered Sequentially ............ 6
Section, and Table 4 .......................................................................... 6 Removed Endnote 1, Table 4; Renumbered Sequentially ............ 6
Changes to Figure 4 .......................................................................... 7 Changes to Table 5 ............................................................................. 8
Changes to Table 7 ............................................................................ 9 Removed Solder Heat Reflow Section and Figure 53;
Changes to Table 8 .......................................................................... 10 Renumbered Sequentially ............................................................. 25
Changes to Terminology Section.................................................. 17
Changes to SPI Serial Data Interface Section ............................. 21 12/2013Revision 0: Initial Version
Rev. D | Page 2 of 28