250 MHz Bandwidth DPD Observation Receiver AD6641 FEATURES GENERAL DESCRIPTION SNR = 65.8 dBFS at f up to 250 MHz at 500 MSPS The AD6641 is a 250 MHz bandwidth digital predistortion IN ENOB of 10.5 bits at f up to 250 MHz at 500 MSPS (1.0 dBFS) IN (DPD) observation receiver that integrates a 12-bit 500 MSPS SFDR = 80 dBc at f up to 250 MHz at 500 MSPS (1.0 dBFS) IN ADC, a 16k 12 FIFO, and a multimode back end that allows Excellent linearity users to retrieve the data through a serial port (SPORT), the SPI DNL = 0.5 LSB typical, INL = 0.6 LSB typical interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS Integrated 16k 12 FIFO port after being stored in the integrated FIFO memory. It is opti- FIFO readback options mized for outstanding dynamic performance and low power 12-bit parallel CMOS at 62.5 MHz consumption and is suitable for use in telecommunications 6-bit DDR LVDS interface applications such as a digital predistortion observation path SPORT at 62.5 MHz where wider bandwidths are desired. All necessary functions, SPI at 25 MHz including the sample-and-hold and voltage reference, are High speed synchronization capability included on the chip to provide a complete signal conversion 1 GHz full power analog bandwidth solution. Integrated input buffer The on-chip FIFO allows small snapshots of time to be captured On-chip reference, no external decoupling required via the ADC and read back at a lower rate. This reduces the Low power dissipation constraints of signal processing by transferring the captured 695 mW at 500 MSPS data at an arbitrary time and at a much lower sample rate. The Programmable input voltage range FIFO can be operated in several user-programmable modes. In 1.18 V to 1.6 V, 1.5 V nominal the single capture mode, the ADC data is captured when sig- 1.9 V analog and digital supply operation naled via the SPI port or the use of the external FILL pins. In 1.9 V or 3.3 V SPI and SPORT operation the continuous capture mode, the data is loaded continuously Clock duty cycle stabilizer into the FIFO and the FILL pins are used to stop this operation. Integrated data clock output with programmable clock and data alignment APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM FILL+ FILL DUMP CLK+ CLOCK AND CONTROL CLK PCLK+ PCLK PARALLEL VIN+ PD 5:0 IN DDR LVDS MODE AND FIFO OR PD 11:0 IN CMOS MODE ADC SPORT 16k 12 VIN SP SCLK OUTPUTS SP SDFS SP SDO SPI CONTROL REFERENCE FULL AND DATA EMPTY VREF SCLK, SDIO, AND CSB Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09813-001AD6641 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance.................................................................... 10 Applications....................................................................................... 1 ESD Caution................................................................................ 10 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 11 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 15 Revision History ............................................................................... 2 Equivalent Circuits......................................................................... 18 Product Highlights ........................................................................... 3 SPI Register Map ............................................................................ 20 Specifications..................................................................................... 4 Theory of Operation ...................................................................... 23 DC Specifications ......................................................................... 4 FIFO Operation.......................................................................... 23 AC Specifications.......................................................................... 5 FIFO Output Interfaces ............................................................. 26 Digital Specifications ................................................................... 6 Configuration Using the SPI..................................................... 27 Switching Specifications .............................................................. 7 Outline Dimensions....................................................................... 28 SPI Timing Requirements ........................................................... 8 Ordering Guide .......................................................................... 28 Absolute Maximum Ratings.......................................................... 10 REVISION HISTORY 4/11Revision 0: Initial Version Rev. 0 Page 2 of 28