Dual IF Receiver AD6642 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND 11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer (NSR) AD6642 DC0AB Performance with NSR enabled 14 11 VIN+A SNR: 75.5 dBFS in 40 MHz band to 70 MHz 185 MSPS PIPELINE NOISE SHAPING D0AB ADC REQUANTIZER VINA SNR: 73.7 dBFS in 60 MHz band to 70 MHz 185 MSPS VCMA Performance with NSR disabled 14 11 VIN+B PIPELINE NOISE SHAPING D10AB SNR: 66.5 dBFS to 70 MHz 185 MSPS ADC REQUANTIZER VINB SFDR: 83 dBc to 70 MHz 185 MSPS VCMB Low power: 0.62 W 185 MSPS MODE REFERENCE 1.8 V analog supply operation CLOCK SYNC DIVIDER 1.8 V LVDS (ANSI-644 levels) output PDWN SERIAL PORT 1-to-8 integer clock divider Internal ADC voltage reference SCLK SDIO CSB CLK+ CLK 1.75 V p-p analog input range (programmable to 2.0 V p-p) Differential analog inputs with 800 MHz bandwidth Figure 1. 95 dB channel isolation/crosstalk PRODUCT HIGHLIGHTS Serial port control User-configurable built-in self-test (BIST) capability 1. Two ADCs are contained in a small, space-saving, Energy-saving power-down modes 10 mm 10 mm 1.4 mm, 144-ball CSP BGA package. 2. Pin selectable noise shaping requantizer (NSR) function APPLICATIONS that allows for improved SNR within a reduced bandwidth Communications of up to 60 MHz at 185 MSPS. Diversity radio and smart antenna (MIMO) systems 3. LVDS digital output interface configured for low cost Multimode digital receivers (3G) FPGA families. WCDMA, LTE, CDMA2000 4. 120 mW per ADC core power consumption. WiMAX, TD-SCDMA 5. Operation from a single 1.8 V supply. I/Q demodulation systems 6. Standard serial port interface (SPI) that supports various General-purpose software radios product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. 7. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems. Rev. 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DATA MULTIPLEXER AND LVDS DRIVERS 08563-001AD6642 TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Standby Mode .................................... 20 Applications....................................................................................... 1 Channel/Chip Synchronization................................................ 20 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 21 Product Highlights ........................................................................... 1 Timing ......................................................................................... 21 Revision History ............................................................................... 2 Noise Shaping Requantizer (NSR) ............................................... 22 General Description ......................................................................... 3 22% BW Mode (>40 MHz 184.32 MSPS)........................... 22 Specifications..................................................................................... 4 33% BW Mode (>60 MHz 184.32 MSPS)........................... 22 DC Specifications ......................................................................... 4 MODE Pin................................................................................... 23 AC Specifications.......................................................................... 5 Built-In Self-Test (BIST) and Output Test .................................. 24 Digital Specifications ................................................................... 6 Built-In Self-Test (BIST)............................................................ 24 Switching Specifications .............................................................. 7 Output Test Modes..................................................................... 24 Timing Specifications .................................................................. 8 Serial Port Interface (SPI).............................................................. 25 Absolute Maximum Ratings............................................................ 9 Configuration Using the SPI..................................................... 25 Thermal Characteristics .............................................................. 9 Hardware Interface..................................................................... 25 ESD Caution.................................................................................. 9 Memory Map .................................................................................. 26 Pin Configuration and Function Descriptions........................... 10 Reading the Memory Map Register Table............................... 26 Typical Performance Characteristics ........................................... 12 Memory Map Register Table..................................................... 27 Equivalent Circuits ......................................................................... 15 Memory Map Register Descriptions........................................ 29 Theory of Operation ...................................................................... 16 Applications Information .............................................................. 30 ADC Architecture ...................................................................... 16 Design Guidelines ...................................................................... 30 Analog Input Considerations.................................................... 16 Outline Dimensions....................................................................... 31 Clock Input Considerations...................................................... 18 Ordering Guide .......................................................................... 31 REVISION HISTORY 7/10Rev. 0 to Rev. A Changes to ADC Architecture Section........................................ 16 Changes to Figure 34 and Figure 35............................................. 18 Changes to Timing Section and Data Clock Output (DCO) Section.............................................................................................. 21 Changes to 22% BW Mode (>40 MHz 184.32 MSPS) Section and 33% BW Mode (>60 MHz 184.32 MSPS) Section ......... 22 Changes to Design Guidelines Section........................................ 30 10/09Revision 0: Initial Version Rev. A Page 2 of 32