Dual IF Receiver Data Sheet AD6643 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD 11-bit, 250 MSPS output data rate per channel Performance with NSR enabled AD6643 DCO SNR: 74.5 dBFS in a 55 MHz band to 90 MHz at 250 MSPS 14 11 VIN+A NOISE SHAPING PIPELINE SNR: 72.0 dBFS in a 82 MHz band to 90 MHz at 250 MSPS D0 REQUANTIZER ADC VINA Performance with NSR disabled VCM SNR: 66.2 dBFS up to 90 MHz at 250 MSPS 14 11 VIN+B NOISE SHAPING PIPELINE D10 SFDR: 85 dBc up to 185 MHz at 250 MSPS REQUANTIZER ADC VINB Total power consumption: 706 mW at 200 MSPS OEB 1.8 V supply voltages REFERENCE CLOCK LVDS (ANSI-644 levels) outputs SYNC DIVIDER Integer 1-to-8 input clock divider (625 MHz maximum input) PDWN SERIAL PORT Internal ADC voltage reference Flexible analog input range SCLK SDIO CSB CLK+ CLK 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) NOTES 1. THE D0 TO D10 PINS REPRESENT BOTH THE CHANNEL A Differential analog inputs with 400 MHz bandwidth AND CHANNEL B LVDS OUTPUT DATA. 95 dB channel isolation/crosstalk Figure 1. Serial port control Energy saving power-down modes APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios GENERAL DESCRIPTION The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel Each ADC output is connected internally to an NSR block. The intermediate frequency (IF) receiver specifically designed to integrated NSR circuitry allows for improved SNR performance in support multi-antenna systems in telecommunication a smaller frequency band within the Nyquist bandwidth. The applications where high dynamic range performance, low power, device supports two different output modes selectable via the SPI. and small size are desired. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6643 supports enhanced SNR per- The device consists of two high performance analog-to-digital formance within a limited portion of the Nyquist bandwidth converters (ADCs) and noise shaping requantizer (NSR) digital while maintaining an 11-bit output resolution. blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and The NSR block can be programmed to provide a bandwidth each ADC features a wide bandwidth switched capacitor sampling of either 22% or 33% of the sample clock. For example, with a network within the first stage of the differential pipeline. An sample clock rate of 185 MSPS, the AD6643 can achieve up to integrated voltage reference eases design considerations. A duty 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and cycle stabilizer (DCS) compensates for variations in the ADC up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode. clock duty cycle, allowing the converters to maintain excellent (continued on Page 3) performance. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com DATA MULTIPLEXER AND LVDS DRIVERS 09638-001AD6643 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 23 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 23 General Description ......................................................................... 1 Power Dissipation and Standby Mode .................................... 24 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 25 Revision History ............................................................................... 2 ADC Overrange (OR) ................................................................ 25 Product Highlights ........................................................................... 3 Noise Shaping Requantizer (NSR) ............................................... 26 Specif icat ions ..................................................................................... 4 22% BW Mode (>40 MHz at 184.32 MSPS) ........................... 26 ADC DC Specifications ................................................................. 4 33% BW Mode (>60 MHz at 184.32 MSPS) ........................... 27 ADC AC Specifications ................................................................. 5 Channel/Chip Synchronization .................................................... 28 Digital SpecificationsAD6643-200/AD6643-250 ..................... 6 Serial Port Interface (SPI) .............................................................. 29 Switching Specifications ................................................................ 8 Configuration Using the SPI ..................................................... 29 Timing SpecificationsAD6643-200/AD6643-250 ................ 8 Hardware Interface ..................................................................... 29 Absolute Maximum Ratings .......................................................... 10 SPI Accessible Features .............................................................. 30 Thermal Characteristics ............................................................ 10 Memory Map .................................................................................. 31 ESD Caution ................................................................................ 10 Reading the Memory Map Register Table ............................... 31 Pin Configurations and Function Descriptions ......................... 11 Memory Map Register Table ..................................................... 32 Typical Performance Characteristics ........................................... 15 Memory Map Register Description ......................................... 35 Equivalent Circuits ......................................................................... 20 Applications Information .............................................................. 36 Theory of Operation ...................................................................... 21 Design Guidelines ...................................................................... 36 ADC Architecture ...................................................................... 21 Outline Dimensions ....................................................................... 37 Analog Input Considerations .................................................... 21 Ordering Guide .......................................................................... 37 REVISION HISTORY 4/2019Rev. C to Rev. D Changes to Table 2 ............................................................................. 5 Changes to General Description Section ...................................... 3 Changes to Table 4 ............................................................................. 8 Changes to Ordering Guide .......................................................... 40 Changes to Figure 2 ........................................................................... 9 Change to OEB Pin Description, Table 8 .................................... 12 11/2012Rev. B to Rev. C Changes Figure 5 and Table 9 ....................................................... 13 Changes to Features Section............................................................ 1 Changes to Typical Performance Characteristics Conditions Change to Table 1 ................................................................................ Summary .......................................................................................... 15 Changes to Table 4 ............................................................................ 8 Added AD6643-200 Throughout ................................................. 15 Changes to Reading the Memory Map Register Table Section ..... 31 Changes to Figure 24 and Figure 25............................................. 18 Deleted Registers 0x0E, 0x24, and 0x25, Table 14 ...................... 33 Changes to Theory of Operation Section.................................... 19 Change to Memory Map Register Description Section............. 36 Changes to Timing Section ........................................................... 23 Updated Outline Dimensions ....................................................... 37 Added ADC Overrange (OR) Section ......................................... 23 Changed Frequency (Hz) to Frequency (MHz) in Figure 39, 6/2012Rev. A to Rev. B Figure 40, and Figure 41 ................................................................ 24 Changes to Features .......................................................................... 1 Changed Frequency (Hz) to Frequency (MHz) in Figure 42, Changes to Full Power Bandwidth Parameter, Deleted Noise Figure 43, and Figure 44 ................................................................ 25 Bandwidth Parameter, Changes to Endnote 3 Table 2................ 6 Changes to Channel/Chip Synchronization Section ................. 26 Added Figure 20 to Figure 33 Renumbered Sequentially ........ 17 Changed 0x59 to 0x3E Throughout ............................................. 29 Changes to Figure 52 ...................................................................... 24 Changes to 0x02, Bits 5:4 and 0x16, Bit 5 in Table 14 ............. 30 Updated Outline Dimensions ....................................................... 35 Deleted 0x59, Table 14 ................................................................... 32 Deleted SYNC Pin Control (Register 0x59) Section .................. 33 9/2011Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 35 Added 250 MSPS Speed Grade Throughout................................. 1 Changes to Table 1 ............................................................................ 4 4/2011Revision 0: Initial Version Rev. D Page 2 of 40