IF Diversity Receiver Data Sheet AD6649 FEATURES APPLICATIONS SNR = 73.0 dBFS in a 95 MHz bandwidth at Communications 185 MHz A and 245.76 MSPS Diversity radio systems IN SFDR = 85 dBc at 185 MHz A and 250 MSPS Multimode digital receivers (3G) IN Noise density = 151.2 dBFS/Hz input at 185 MHz, 1 dBFS TD-SCDMA, WiMax, WCDMA, A and 250 MSPS CDMA2000, GSM, EDGE, LTE IN Total power consumption: 1 W with fixed-frequency NCO, General-purpose software radios 95 MHz FIR filter Broadband data applications 1.8 V supply voltages GENERAL DESCRIPTION LVDS (ANSI-644 levels) outputs The AD6649 is a mixed-signal intermediate frequency (IF) receiver Integer 1-to-8 input clock divider (625 MHz maximum input) consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital Integrated dual-channel ADC downconverter (DDC). The AD6649 is designed to support Sample rates of up to 250 MSPS communications applications, where low cost, small size, wide IF sampling frequencies to 400 MHz bandwidth, and versatility are desired. Internal ADC voltage reference Flexible input range The dual ADC cores feature a multistage, differential pipelined 1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal) architecture with integrated output error correction logic. Each ADC clock duty cycle stabilizer ADC features wide bandwidth inputs supporting a variety of 95 dB channel isolation/crosstalk user-selectable input ranges. An integrated voltage reference Integrated wideband digital processor eases design considerations. A duty cycle stabilizer is provided to 32-bit complex numerically controlled oscillator (NCO) compensate for variations in the ADC clock duty cycle, allowing FIR filter with 2 modes the converters to maintain excellent performance. Real output from an f /4 output NCO S Amplitude detect bits for efficient AGC implementation Energy saving power-down modes Decimated, interleaved real LVDS data outputs FUNCTIONAL BLOCK DIAGRAM AVDD FDA DRVDD AD6649 THRESHOLD DETECT I SELECTABLE FIR OR+ FILTER VIN+A OR ADC DIGITAL D13+/D13 INTERLEAVING VINA Q SELECTABLE FIR DC D0+/D0 FILTER CORRECTION REFERENCE 32-BIT CLK+ f /4 DIVIDE 1 S TUNING NCO TO 8 NCO CLK DUTY DCO+ DCO DC Q CYCLE SELECTABLE GENERATION CORRECTION STABILIZER DCO FIR FILTER MULTICHIP VINB SYNC SYNC ADC VIN+B PROGRAMMING DATA I SELECTABLE FIR FILTER THRESHOLD DETECT SPI AGND FDB PDWN OEB SDIO SCLK CSB Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DDR LVDS OUTPUT BUFFER 09635-001AD6649 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 NCO and FIR Filter Modes ....................................................... 22 Applications ....................................................................................... 1 fS/4 Fixed-Frequency NCO ....................................................... 22 General Description ......................................................................... 1 Numerically Controlled Oscillator (NCO) ................................. 23 Functional Block Diagram .............................................................. 1 Frequency Translation ............................................................... 23 Revision History ............................................................................... 2 NCO Synchronization ............................................................... 23 Product Highlights ........................................................................... 3 NCO Amplitude and Phase Dither .......................................... 23 Specifications ..................................................................................... 4 FIR Filters ........................................................................................ 24 ADC DC Specifications ............................................................... 4 FIR Synchronization .................................................................. 24 ADC AC Specifications ............................................................... 5 Filter Performance ...................................................................... 24 Digital Specifications ................................................................... 6 Output NCO ............................................................................... 25 Switching Specifications .............................................................. 8 ADC Overrange and Gain Control .............................................. 26 Timing Specifications .................................................................. 9 ADC Overrange (OR) ................................................................ 26 Absolute Maximum Ratings .......................................................... 10 Gain Switching ............................................................................ 26 Thermal Characteristics ............................................................ 10 DC Correction ................................................................................ 27 ESD Caution ................................................................................ 10 Channel/Chip Synchronization .................................................... 28 Pin Configuration and Function Descriptions ........................... 11 Serial Port Interface (SPI) .............................................................. 29 Typical Performance Characteristics ........................................... 13 Configuration Using the SPI ..................................................... 29 Equivalent Circuits ......................................................................... 16 Hardware Interface ..................................................................... 29 Theory of Operation ...................................................................... 17 SPI Accessible Features .............................................................. 30 ADC Architecture ...................................................................... 17 Memory Map .................................................................................. 31 Analog Input Considerations .................................................... 17 Reading the Memory Map Register Table ............................... 31 Voltage Reference ....................................................................... 19 Memory Map Register Table ..................................................... 32 Clock Input Considerations ...................................................... 19 Memory Map Register Description ......................................... 36 Power Dissipation and Standby Mode ..................................... 20 Applications Information .............................................................. 39 Digital Outputs ........................................................................... 21 Design Guidelines ...................................................................... 39 Overrange (OR) .......................................................................... 21 Outline Dimensions ....................................................................... 40 Digital Processing ........................................................................... 22 Ordering Guide .......................................................................... 40 Numerically Controlled Oscillator (NCO) ............................. 22 REVISION HISTORY 1/14Rev. B to Rev. C Change to Memory Map Register Description Section ............. 36 Updated Outline Dimensions ........................................................ 40 Changes to FIR Filters Section ....................................................... 24 Added Table 12 Renumbered Sequentially ................................. 24 9/11Rev. 0 to Rev. A Changes to Figure 43 and Figure 44 .............................................. 25 Changes to Table 1 ............................................................................. 4 Changes to Table 3 ............................................................................. 6 1/13Rev. A to Rev. B Changes to Table 4 ............................................................................. 8 Change to Features Section .............................................................. 1 Changes to Table 8 .......................................................................... 11 Change to Input Referred Noise Parameter, Table 1 ..................... 4 Added Overrange (OR) Section ................................................... 21 Changes to Table 2 ............................................................................. 5 Changes to Channel/Chip Synchronization Section ................. 28 Change to Logic Input/Output (SDIO) Parameter, Table 3 ......... 6 Change to the NCO/FIR SYNC Pin Control (Register 0x59) .. 38 Changes to Table 4 ............................................................................. 8 4/11Revision 0: Initial Version Change to Reading the Register Memory Map Table Section ....... 31 Changes to Table 15 ......................................................................... 33 Rev. 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