/ / / 12-Bit, 65 MSPS IF to Baseband Diversity Receiver AD6652 FEATURES APPLICATIONS SNR = 90 dB in 150 kHz bandwidth (to Nyquist Communications 61.44 MSPS) Diversity radio systems Worst harmonic = 83 dBc (to Nyquist 61.44 MSPS) Multimode digital receivers: Integrated dual-channel ADC: GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE, Sample rates up to 65 MSPS IS95, IS136, CDMA2000, IMT-2000 IF sampling frequencies to 200 MHz I/Q demodulation systems Internal ADC voltage reference Smart antenna systems Integrated ADC sample-and-hold inputs General-purpose software radios Flexible analog input range (1 V to 2 V p-p) Broadband data applications Differential analog inputs Instrumentation and test equipment ADC clock duty cycle stabilizer 85 dB channel isolation/crosstalk Integrated wideband digital downconverter (DDC): Crossbar switched DDC inputs Digital resampling for noninteger decimation Programmable decimating FIR filters Flexible control for multicarrier and phased array Dual AGC stages for output level control Dual 16-bit parallel or 8-bit link output ports User-configurable built-in self-test (BIST) capability Energy-saving power-down modes FUNCTIONAL BLOCK DIAGRAM DUAL-CHANNEL 12-BIT A/D FRONT END WIDEBAND DIGITAL DOWNCONVERTER (DDC) RAM RCIC2 PORT A VINA+ TO OUTPUT PORTS 12 CIC5 COEF. ADC CHANNEL A RESAMPLER SHA CHANNEL / FILTER 8-BIT DSP A VINA LINK CHANNEL 0 RCF OUTPUTS OTRA NCO CHANNELS 0, 1, 2, 3 OR LIA REFTA LIA RAM 16-BIT RCIC2 REFBA CIC5 TO OUTPUT PORTS COEF. PARALLEL RESAMPLER PSEUDO FILTER OUTPUT VREF RANDOM CHANNEL 1 VREF CONTROL SENSE NOISE NCO AGC A* SEQUENCE OUTPUT REFTB RAM MUX RCIC2 TO OUTPUT CIC5 COEF. LIB CIRCUITRY REFBB RESAMPLER PORTS FILTER LIB PORT B CHANNEL 2 OTRB NCO VINB+ 12 AGC B* ADC 8-BIT DSP CHANNEL SHA / RAM B CHANNEL B LINK VINB RCIC2 TO OUTPUT PORTS CIC5 COEF. RESAMPLER OR FILTER RCF OUTPUTS 16-BIT CHANNEL 3 CHANNELS 0, 1, 2, 3 NCO PARALLEL OUTPUT *DATA INTERLEAVING AND INTERPOLATING HB FILTER CONTROL CLOCK SYNCA EXTERNAL PDWN DUTY BUILT-IN MODE ACLK DDC PROGRAM SYNCB SYNC. CYCLE SELF-TEST SELECT SYNCC CLK MICROPORT SHRDREF DUTYEN CIRCUIT STABILIZER CIRCUITRY SYNCD 83 3 +3.0AVDD +3.3VDDIO 2.5VDD AGND DGND CLK DATA CONT ADD Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. 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INPUT MATRIX 03198-0-001AD6652 TABLE OF CONTENTS Product Description......................................................................... 4 Gain Switching............................................................................ 31 Product Highlights ....................................................................... 4 Numerically Controlled Oscillator............................................... 33 Specifications..................................................................................... 5 Frequency Translation to Baseband......................................... 33 Recommended Operating Conditions ...................................... 5 NCO Shadow Register............................................................... 33 ADC DC Specifications............................................................... 5 NCO Frequency Hold-Off Register......................................... 33 ADC Switching Specifications.................................................... 5 Phase Offset................................................................................. 33 ADC AC Specifications ............................................................... 6 NCO Control Register ............................................................... 33 Electrical Characteristics............................................................. 7 Second-Order rCIC Filter ............................................................. 35 General Timing Characteristics ................................................. 8 rCIC2 Scale Factor ..................................................................... 35 Microprocessor Port Timing Characteristics ........................... 9 rCIC2 Output Level ................................................................... 36 Absolute Maximum Ratings.......................................................... 10 rCIC2 Rejection.......................................................................... 36 Thermal Characteristics ............................................................ 10 Decimation and Interpolation Registers ................................. 36 Test Level ..................................................................................... 10 rCIC2 Scale Register .................................................................. 36 ESD Caution................................................................................ 10 Fifth-Order CIC Filter ................................................................... 37 Pin Configuration and Function Descriptions........................... 11 CIC5 Rejection ........................................................................... 37 Typical Performance Characteristics ........................................... 14 RAM Coefficient Filter .................................................................. 38 DDC Timing Diagrams ................................................................. 17 RCF Decimation Register.......................................................... 38 Terminology .................................................................................... 23 RCF Decimation Phase.............................................................. 38 ADC Equivalent Circuits........................................................... 23 RCF Filter Length....................................................................... 38 Theory of Operation ...................................................................... 24 RCF Output Scale Factor and Control Register ..................... 39 ADC Architecture ...................................................................... 24 Interpolating Half-Band Filters .................................................... 40 Digital Downconverter Architecture Overview ......................... 29 Automatic Gain Control................................................................ 41 Data Input Matrix....................................................................... 29 AGC Loop ................................................................................... 41 Numerically Controlled Oscillator........................................... 29 Desired Signal Level Mode........................................................ 41 Second-Order rCIC Filter ......................................................... 29 Synchronization.......................................................................... 44 Fifth-Order CIC Filter ............................................................... 29 User-Configurable Built-In Self-Test (BIST) .............................. 45 RAM Coefficient Filter .............................................................. 29 RAM BIST................................................................................... 45 Interpolating Half-Band Filters and AGC............................... 29 Channel BIST.............................................................................. 45 Control Register and Memory Map Address Notation ............. 31 Channel/Chip Synchronization.................................................... 46 DDC Input Matrix...................................................................... 31 Start .............................................................................................. 46 DDC Data Latency ..................................................................... 31 Hop............................................................................................... 48 Rev. 0 Page 2 of 76