AD6655ABCPZ-125 Analog Devices

IF Diversity Receiver Data Sheet AD6655 FEATURES APPLICATIONS SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at Communications 70 MHz at 150 MSPS Diversity radio systems SFDR = 80 dBc to 70 MHz at 150 MSPS Multimode digital receivers (3G) 1.8 V analog supply operation TD-SCDMA, WiMax, WCDMA, 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS CDMA2000, GSM, EDGE, LTE output supply I/Q demodulation systems Integer 1-to-8 input clock divider Smart antenna systems Integrated dual-channel ADC General-purpose software radios Sample rates up to 150 MSPS Broadband data applications IF sampling frequencies to 450 MHz PRODUCT HIGHLIGHTS Internal ADC voltage reference Integrated ADC sample-and-hold inputs 1. Integrated dual, 14-bit, 150 MSPS ADC. Flexible analog input range: 1 V p-p to 2 V p-p 2. Integrated wideband decimation filter and 32-bit ADC clock duty cycle stabilizer complex NCO. 95 dB channel isolation/crosstalk 3. Fast overrange detect and signal monitor with serial output. Integrated wideband digital downconverter (DDC) 4. Proprietary differential input maintains excellent SNR 32-bit complex, numerically controlled oscillator (NCO) performance for input frequencies up to 450 MHz. Decimating half-band filter and FIR filter 5. Flexible output modes, including independent CMOS, Supports real and complex output modes interleaved CMOS, IQ mode CMOS, and interleaved LVDS. Fast attack/threshold detect bits 6. SYNC input allows synchronization of multiple devices. Composite signal monitor 7. 3-bit SPI port for register programming and register readback. Energy-saving power-down modes FUNCTIONAL BLOCK DIAGRAM AVDD FD 0:3 A DVDD DRVDD FD BITS/THRESHOLD AD6655 DETECT I VIN+A D13A LP/HP SHA ADC DECIMATING VINA HB FILTER + D0A Q FIR VREF CLK+ DIVIDE 1 TO 8 32-BIT CLK SENSE SIGNAL f /8 ADC TUNING MONITOR NCO NCO DUTY DCOA DCO CML REF CYCLE GENERATION SELECT STABILIZER DCOB RBIAS Q LP/HP D13B VINB DECIMATING SHA ADC HB FILTER + VIN+B FIR I PROGRAMMING DATA D0B MULTI-CHIP FD BITS/THRESHOLD SIGNAL MONITOR SIGNAL MONITOR SPI SYNC DETECT DATA INTERFACE AGND SYNC FD 0:3 B SMI SMI SMI SDIO/ SCLK/ CSB DRGND SDFS SCLK/ SDO/ DCS DFS PDWN OEB NOTES 1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY SEE FIGURE 10 FOR LVDS PIN NAMES. Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. CMOS CMOS/LVDS OUTPUT BUFFER OUTPUT BUFFER 06709-001AD6655 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Decimating Half-Band Filter and FIR filter ................................ 39 Applications ....................................................................................... 1 Half-Band Filter Coefficients .................................................... 39 Product Highlights ........................................................................... 1 Half-Band Filter Features .......................................................... 39 Functional Block Diagram .............................................................. 1 Fixed-Coefficient FIR Filter ...................................................... 39 Revision History ............................................................................... 3 Synchronization .......................................................................... 40 General Description ......................................................................... 4 Combined Filter Performance .................................................. 40 Specifications ..................................................................................... 5 Final NCO ................................................................................... 40 ADC DC SpecificationsAD6655-80/AD6655-105 .............. 5 ADC Overrange and Gain Control .............................................. 41 ADC DC SpecificationsAD6655-125/AD6655-150 ............ 6 Fast Detect Overview ................................................................. 41 ADC AC SpecificationsAD6655-80/AD6655-105 ............... 7 ADC Fast Magnitude ................................................................. 41 ADC AC SpecificationsAD6655-125/AD6655-150 ............. 8 ADC Overrange (OR) ................................................................ 42 Digital SpecificationsAD6655-80/AD6655-105 ................... 9 Gain Switching ............................................................................ 42 Digital SpecificationsAD6655-125/AD6655-150 ............... 11 Signal Monitor ................................................................................ 44 Switching SpecificationsAD6655-80/AD6655-105 ............ 13 Peak Detector Mode................................................................... 44 Switching SpecificationsAD6655-125/AD6655-150 ......... 14 RMS/MS Magnitude Mode ....................................................... 44 Timing Specifications ................................................................ 15 Threshold Crossing Mode ......................................................... 45 Absolute Maximum Ratings .......................................................... 18 Additional Control Bits ............................................................. 45 Thermal Characteristics ............................................................ 18 DC Correction ............................................................................ 45 ESD Caution ................................................................................ 18 Signal Monitor SPORT Output ................................................ 46 Pin Configurations and Function Descriptions ......................... 19 Channel/Chip Synchronization .................................................... 47 Equivalent Circuits ......................................................................... 23 Serial Port Interface (SPI) .............................................................. 48 Typical Performance Characteristics ........................................... 24 Configuration Using the SPI ..................................................... 48 Theory of Operation ...................................................................... 29 Hardware Interface ..................................................................... 48 ADC Architecture ...................................................................... 29 Configuration Without the SPI ................................................ 49 Analog Input Considerations .................................................... 29 SPI Accessible Features .............................................................. 49 Voltage Reference ....................................................................... 31 Memory Map .................................................................................. 50 Clock Input Considerations ...................................................... 32 Reading the Memory Map Register Table ............................... 50 Power Dissipation and Standby Mode ..................................... 34 Memory Map Register Table ..................................................... 51 Digital Outputs ........................................................................... 35 Memory Map Register Description ......................................... 55 Digital Downconverter .................................................................. 37 Applications Information .............................................................. 59 Downconverter Modes .............................................................. 37 Design Guidelines ...................................................................... 59 Numerically Controlled Oscillator (NCO) ............................. 37 Evaluation Board ............................................................................ 61 Half-Band Decimating Filter and FIR Filter ........................... 37 Power Supplies ............................................................................ 61 fADC/8 Fixed-Frequency NCO ................................................... 37 Input Signals................................................................................ 61 Numerically Controlled Oscillator (NCO) ................................. 38 Output Signals ............................................................................ 61 Frequency Translation ............................................................... 38 Default Operation and Jumper Selection Settings ................. 62 NCO Synchronization ............................................................... 38 Alternative Clock Configurations ............................................ 62 Phase Offset ................................................................................. 38 Alternative Analog Input Drive Configuration...................... 63 NCO Amplitude and Phase Dither .......................................... 38 Schematics ................................................................................... 64 Rev. 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