Quad IF Receiver Data Sheet AD6657A FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND 11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer AD6657A Performance with NSR enabled DCOAB 14 11 VIN+A SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS PIPELINE NOISE SHAPING DOAB ADC REQUANTIZER VINA SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS PORT A VCMA SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS 14 11 VIN+B PIPELINE NOISE SHAPING D10AB Performance with NSR disabled ADC REQUANTIZER VINB SNR: 66.5 dBFS to 70 MHz at 185 MSPS VCMB DCOCD SFDR: 88 dBc to 70 MHz at 185 MSPS 14 11 VIN+C PIPELINE NOISE SHAPING DOCD ADC REQUANTIZER Low power: 1.2 W at 185 MSPS VINC PORT B 1.8 V analog supply operation VCMC 14 11 VIN+D 1.8 V LVDS (ANSI-644 levels) output NOISE SHAPING PIPELINE D10CD REQUANTIZER ADC VIND 1-to-8 integer clock divider VCMD Internal ADC voltage reference MODE REFERENCE 1.75 V p-p analog input range (programmable to 2.0 V p-p) CLOCK SYNC DIVIDER Differential analog inputs with 800 MHz bandwidth PDWN 95 dB channel isolation/crosstalk SERIAL PORT Serial port control User-configurable built-in self test (BIST) capability SCLK SDIO CSB CLK+ CLK Energy saving power-down modes Figure 1. APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios Each ADC output is connected internally to an NSR block. The GENERAL DESCRIPTION integrated NSR circuitry allows for improved SNR performance in The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate a smaller frequency band within the Nyquist bandwidth. The frequency (IF) receiver specifically designed to support multiple device supports two different output modes selectable via the antenna systems in telecommunication applications where high external MODE pin or the serial port interface (SPI). dynamic range performance, low power, and small size are desired. With the NSR feature enabled, the outputs of the ADCs are The device consists of four high performance ADCs and NSR processed such that the AD6657A supports enhanced SNR per- digital blocks. Each ADC consists of a multistage, differential formance within a limited portion of the Nyquist bandwidth while pipelined architecture with integrated output error correction maintaining an 11-bit output resolution. The NSR block can be logic. The ADC features a wide bandwidth switched capacitor programmed to provide a bandwidth of either 22%, 33%, or 36% of sampling network within the first stage of the differential pipeline. the sample clock. For example, with a sample clock rate of An integrated voltage reference eases design considerations. A 185 MSPS, the AD6657A can achieve up to 76.0 dBFS SNR for a duty cycle stabilizer (DCS) compensates for variations in the 40 MHz bandwidth in the 22% mode, up to 73.6 dBFS SNR for a ADC clock duty cycle, allowing the converters to maintain 60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS SNR for a excellent performance. 65 MHz bandwidth in the 36% mode. (General Description continued on Page 3) Rev. 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DATA MULTIPLEXER AND LVDS DRIVERS 09684-001AD6657A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Channel/Chip Synchronization ................................................ 23 Applications ....................................................................................... 1 Digital Outputs ........................................................................... 24 Functional Block Diagram .............................................................. 1 Timing.......................................................................................... 24 General Description ......................................................................... 1 Noise Shaping Requantizer ........................................................... 25 Revision History ............................................................................... 2 22% BW Mode (>40 MHz at 184.32 MSPS) ........................... 25 Product Highlights ........................................................................... 3 33% BW Mode (>60 MHz at 184.32 MSPS) ........................... 26 Specifications ..................................................................................... 4 36% BW Mode (>65 MHz at 184.32 MSPS) ........................... 27 DC Specifications ......................................................................... 4 MODE Pin ................................................................................... 27 AC Specifications .......................................................................... 5 Built-In Self Test (BIST) and Output Test ................................... 28 Digital Specifications ................................................................... 7 BIST .............................................................................................. 28 Switching Specifications .............................................................. 9 Output Test Modes ..................................................................... 28 Timing Specifications ................................................................ 10 Serial Port Interface (SPI) .............................................................. 29 Absolute Maximum Ratings ..................................................... 11 Configuration Using the SPI ..................................................... 29 Thermal Characteristics ............................................................ 11 Hardware Interface ..................................................................... 29 ESD Caution ................................................................................ 11 Memory Map .................................................................................. 30 Pin Configuration and Function Descriptions ........................... 12 Reading the Memory Map Register Table ............................... 30 Typical Performance Characteristics ........................................... 14 Memory Map Register Table ..................................................... 31 Equivalent Circuits ......................................................................... 18 Memory Map Register Descriptions ........................................ 33 Theory of Operation ...................................................................... 19 Applications Information .............................................................. 35 ADC Architecture ...................................................................... 19 Design Guidelines ...................................................................... 35 Analog Input Considerations .................................................... 19 Packaging and Ordering Information ......................................... 36 Clock Input Considerations ...................................................... 21 Outline Dimensions ................................................................... 36 Power Dissipation and Standby Mode ..................................... 23 Ordering Guide .......................................................................... 36 REVISION HISTORY 2/14Rev. 0 to Rev. A Changed DCO to Data Skew (t ) Parameter Unit from ns to SKEW ps, Table 4 .......................................................................................... 9 10/11Revision 0: Initial Version Rev. A Page 2 of 36