Quad IF Receiver Data Sheet AD6657 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND 11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer (NSR) AD6657 Performance with NSR enabled DC0AB 14 11 VIN+A SNR: 75.5 dBFS in 40 MHz band to 70 MHz 185 MSPS PIPELINE NOISE SHAPING D0AB ADC REQUANTIZER VINA SNR: 73.7 dBFS in 60 MHz band to 70 MHz 185 MSPS PORT A VCMA Performance with NSR disabled 14 11 VIN+B NOISE SHAPING PIPELINE D10AB SNR: 66.5 dBFS to 70 MHz 185 MSPS REQUANTIZER ADC VINB SFDR: 83 dBc to 70 MHz 185 MSPS VCMB DC0CD Low power: 1.2 W 185 MSPS 14 11 VIN+C NOISE SHAPING PIPELINE D0CD REQUANTIZER 1.8 V analog supply operation ADC VINC PORT B 1.8 V LVDS (ANSI-644 levels) output VCMC 14 11 1-to-8 integer clock divider VIN+D NOISE SHAPING PIPELINE D10CD REQUANTIZER ADC VIND Internal ADC voltage reference VCMD 1.75 V p-p analog input range (programmable to 2.0 V p-p) MODE REFERENCE Differential analog inputs with 800 MHz bandwidth CLOCK SYNC DIVIDER 95 dB channel isolation/crosstalk PDWN Serial port control SERIAL PORT User-configurable built-in self-test (BIST) capability Energy-saving power-down modes SCLK SDIO CSB CLK+ CLK Figure 1. APPLICATIONS Communications PRODUCT HIGHLIGHTS Diversity radio and smart antenna (MIMO) systems 1. Four ADCs are contained in a small, space-saving, Multimode digital receivers (3G) 10 mm 10 mm 1.4 mm, 144-ball CSP BGA package. WCDMA, LTE, CDMA2000 2. Pin selectable noise shaping requantizer (NSR) function WiMAX, TD-SCDMA that allows for improved SNR within a reduced bandwidth I/Q demodulation systems of up to 60 MHz at 185 MSPS. General-purpose software radios 3. LVDS digital output interface configured for low cost FPGA families. 4. 230 mW per ADC core power consumption. 5. Operation from a single 1.8 V supply. 6. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. 7. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems. Rev. 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DATA MULTIPLEXER AND LVDS DRIVERS 08557-001AD6657 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Standby Mode .................................... 20 Applications....................................................................................... 1 Channel/Chip Synchronization................................................ 20 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 21 Product Highlights ........................................................................... 1 Timing ......................................................................................... 21 Revision History ............................................................................... 2 Noise Shaping Requantizer (NSR) ............................................... 22 General Description ......................................................................... 3 22% BW Mode (>40 MHz 184.32 MSPS)........................... 22 Specifications..................................................................................... 4 33% BW Mode (>60 MHz 184.32 MSPS)........................... 22 DC Specifications ......................................................................... 4 MODE Pin................................................................................... 23 AC Specifications.......................................................................... 5 Built-In Self-Test (BIST) and Output Test .................................. 24 Digital Specifications ................................................................... 6 Built-In Self-Test (BIST)............................................................ 24 Switching Specifications .............................................................. 7 Output Test Modes..................................................................... 24 Timing Specifications .................................................................. 8 Serial Port Interface (SPI).............................................................. 25 Absolute Maximum Ratings............................................................ 9 Configuration Using the SPI..................................................... 25 Thermal Characteristics .............................................................. 9 Hardware Interface..................................................................... 25 ESD Caution.................................................................................. 9 Memory Map .................................................................................. 26 Pin Configuration and Function Descriptions........................... 10 Reading the Memory Map Register Table............................... 26 Typical Performance Characteristics ........................................... 12 Memory Map Register Table..................................................... 27 Equivalent Circuits ......................................................................... 15 Memory Map Register Descriptions........................................ 29 Theory of Operation ...................................................................... 16 Applications Information .............................................................. 30 ADC Architecture ...................................................................... 16 Design Guidelines ...................................................................... 30 Analog Input Considerations.................................................... 16 Outline Dimensions....................................................................... 31 Clock Input Considerations...................................................... 18 Ordering Guide .......................................................................... 31 REVISION HISTORY 8/11Rev. A to Rev. B 7/10Rev. 0 to Rev. A Changes to Logic Input/Output (SDIO) Parameter Note, Changes to ADC Architecture Section........................................ 16 Table 3 ................................................................................................ 6 Changes to Figure 34 and Figure 35............................................. 18 Added Wake-Up Time (from Standby) Parameter, Table 4 and Changes to Timing Section and Data Clock Output (DCO) Section.............................................................................................. 21 Wake-Up Time (from Power Down) Parameter, Table 4............ 7 Changes to Figure 2.......................................................................... 8 Changes to 22% BW Mode (>40 MHz 184.32 MSPS) Section Changes to Table 11........................................................................ 21 and 33% BW Mode (>60 MHz 184.32 MSPS) Section ......... 22 Updated Outline Dimensions ....................................................... 31 Changed 0x0C to 0x79, Address 0x01, Table 13......................... 27 Changed DCO Output Delay (Global) to DCO Output Delay (Local), Address 0x17, Table 13.................................................... 28 Changes to Design Guidelines Section........................................ 30 10/09Revision 0: Initial Version Rev. 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