IF Receiver Data Sheet AD6672 FEATURES GENERAL DESCRIPTION 11-bit, 250 MSPS output data rate The AD6672 is an 11-bit intermediate receiver with sampling Performance with NSR enabled speeds of up to 250 MSPS. The AD6672 is designed to support SNR: 75.2 dBFS in a 55 MHz band to 185 MHz at 250 MSPS communications applications, where low cost, small size, wide SNR: 72.8 dBFS in an 82 MHz band to 185 MHz at 250 MSPS bandwidth, and versatility are desired. Performance with NSR disabled The ADC core features a multistage, differential pipelined SNR: 66.4 dBFS up to 185 MHz at 250 MSPS architecture with integrated output error correction logic. The SFDR: 87 dBc up to 185 MHz at 250 MSPS ADC features wide bandwidth inputs supporting a variety of Total power consumption: 358 mW at 250 MSPS user-selectable input ranges. An integrated voltage reference 1.8 V supply voltages eases design considerations. A duty cycle stabilizer is provided LVDS (ANSI-644 levels) outputs to compensate for variations in the ADC clock duty cycle, Integer 1-to-8 input clock divider (625 MHz maximum input) allowing the converters to maintain excellent performance. Internal ADC voltage reference The ADC core output is connected internally to a noise shaping Flexible analog input range requantizer (NSR) block. The device supports two output modes 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) that are selectable via the serial port interface (SPI). With the Serial port control NSR feature enabled, the outputs of the ADCs are processed such Energy saving power-down modes that the AD6672 supports enhanced SNR performance within a APPLICATIONS limited region of the Nyquist bandwidth while maintaining an Communications 11-bit output resolution. The NSR block is programmed to provide Diversity radio and smart antenna (MIMO) systems a bandwidth of up to 33% of the sample clock. For example, with Multimode digital receivers (3G) a sample clock rate of 250 MSPS, the AD6672 can achieve up to WCDMA, LTE, CDMA2000 73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN. WiMAX, TD-SCDMA With the NSR block disabled, the ADC data is provided directly I/Q demodulation systems to the output with an output resolution of 11 bits. The AD6672 General-purpose software radios can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DCO VIN+ NOISE SHAPED 14 11 PIPELINE REQUANTIZER 0/D0 ADC VIN (NSR) DATA VCM MULITIPLEXER AND LVDS DRIVERS AD6672 D9/D10 OR REFERENCE 1-TO-8 CLOCK SERIAL PORT DIVIDER SCLK SDIO CSB CLK+ CLK Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09997-001AD6672 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 18 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 18 General Description ......................................................................... 1 Power Dissipation and Standby Mode .................................... 19 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 20 Revision History ............................................................................... 2 ADC Overrange (OR) ................................................................ 20 Product Highlights ........................................................................... 3 Noise Shaping Requantizer ........................................................... 21 Specif icat ions ..................................................................................... 4 22% BW NSR Mode (55 MHz BW at 250 MSPS) ..................... 21 ADC DC Specifications ............................................................... 4 33% BW NSR Mode (>82 MHz BW at 250 MSPS) ............... 21 Serial Port Interface (SPI) .............................................................. 23 ADC AC Specifications ............................................................... 5 Digital Specifications ................................................................... 7 Configuration Using the SPI ..................................................... 23 Switching Specifications .............................................................. 8 Hardware Interface ..................................................................... 23 Timing Specifications .................................................................. 9 SPI Accessible Features .............................................................. 24 Absolute Maximum Ratings .......................................................... 10 Memory Map .................................................................................. 25 Thermal Characteristics ............................................................ 10 Reading the Memory Map Register Table ............................... 25 ESD Caution ................................................................................ 10 Memory Map Register Table ..................................................... 26 Pin Configurations and Function Descriptions ......................... 11 Memory Map Register Description ......................................... 28 Typical Performance Characteristics ........................................... 12 Applications Information .............................................................. 29 Equivalent Circuits ......................................................................... 15 Design Guidelines ...................................................................... 29 Theory of Operation ...................................................................... 16 Outline Dimensions ....................................................................... 30 ADC Architecture ...................................................................... 16 Ordering Guide .......................................................................... 30 Analog Input Considerations .................................................... 16 REVISION HISTORY 12/14Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to 33% BW NSR Mode (>82 MHz BW at 250 MSPS) Section .............................................................................................. 21 Changes to Reading the Memory Map Register Table Section .... 25 Changes to Table 13 ........................................................................ 26 Change to Memory Map Register Description Section............. 28 7/14Rev. A to Rev. B Changes to Features Section and Figure 1 ..................................... 1 Changes to Full Power Bandwidth Parameter, Table 2 ................ 6 Deleted Noise Bandwidth Parameter, Table 2 ............................... 6 11/12Rev. 0 to Rev. A Changes to Features Section............................................................ 1 7/11Revision 0: Initial Version Rev. C Page 2 of 30