80 MHz Bandwidth, Dual IF Receiver Data Sheet AD6673 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and AD6673 250 MSPS with NSR set to 33% VIN+A PIPELINE NSR JESD-204B SERDOUT0 Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz 11-BIT ADC INTERFACE VINA CML, TX AIN and 250 MSPS OUTPUTS VCM HIGH SPEED Total power consumption: 707 mW at 250 MSPS SERIALIZERS SERDOUT1 VIN+B PIPELINE NSR 11-BIT ADC 1.8 V supply voltages VINB Integer 1-to-8 input clock divider CMOS DIGITAL PDWN Sample rates of up to 250 MSPS INPUT CONTROL REGISTERS IF sampling frequencies of up to 400 MHz SYSREF SYNCINB CLOCK Internal analog-to-digital converter (ADC) voltage reference GENERATION CMOS FDA CLK FAST DIGITAL DETECT FDB RFCLK OUTPUT CMOS Flexible analog input range DIGITAL INPUT/OUTPUT 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) RST SDIO SCLK CS 95 dB channel isolation/crosstalk Figure 1. Serial port control Energy saving power-down modes APPLICATIONS Communications PRODUCT HIGHLIGHTS Diversity radio and smart antenna (MIMO) systems 1. The configurable JESD204B output block with an integrated Multimode digital receivers (3G) phase-locked loop (PLL) to support up to 5 Gbps per lane TD-SCDMA, WiMAX, WCDMA, with up to two lanes. CDMA2000, GSM, EDGE, LTE I/Q demodulation systems 2. IF receiver includes two, 11-bit, 250 MSPS ADCs with General-purpose software radios programmable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of 22% or 33% of the sample rate. 3. Support for an optional RF clock input to ease system board design. 4. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. 5. An on-chip integer, 1-to-8 input clock divider and SYNC input allows synchronization of multiple devices. 6. Operation from a single 1.8 V power supply. 7. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration. This product may be protected by one or more U.S. or international patents. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 10632-001AD6673 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 33% Bandwidth Mode (>60 MHz at 184.32 MSPS) .............. 25 Applications ....................................................................................... 1 Digital Outputs ............................................................................... 26 Functional Block Diagram .............................................................. 1 JESD204B Transmit Top Level Description ............................ 26 Product Highlights ........................................................................... 1 JESD204B Overview .................................................................. 26 Revision History ............................................................................... 3 Synchronization .......................................................................... 27 General Description ......................................................................... 4 ADC Overrange and Gain Control .......................................... 33 Specifications ..................................................................................... 5 ADC Overrange (OR) ................................................................ 33 ADC DC Specifications ............................................................... 5 Gain Switching ............................................................................ 33 ADC AC Specifications ............................................................... 6 DC Correction ................................................................................ 35 Digital Specifications ................................................................... 7 DC Correction Bandwidth ........................................................ 35 Switching Specifications .............................................................. 9 DC Correction Readback .......................................................... 35 Timing Specifications ................................................................ 10 DC Correction Freeze ................................................................ 35 Absolute Maximum Ratings .......................................................... 11 DC Correction (DCC) Enable Bits .......................................... 35 Thermal Characteristics ............................................................ 11 Serial Port Interface (SPI) .............................................................. 36 ESD Caution ................................................................................ 11 Configuration Using the SPI ..................................................... 36 Pin Configuration and Function Descriptions ........................... 12 Hardware Interface ..................................................................... 36 Typical Performance Characteristics ........................................... 14 SPI Accessible Features .............................................................. 37 Equivalent Circuits ......................................................................... 16 Memory Map .................................................................................. 38 Theory of Operation ...................................................................... 18 Reading the Memory Map Register Table ............................... 38 ADC Architecture ...................................................................... 18 Memory Map Register Table ..................................................... 39 Analog Input Considerations .................................................... 18 Memory Map Register Description ......................................... 43 Voltage Reference ....................................................................... 20 Applications Information .............................................................. 44 Clock Input Considerations ...................................................... 20 Design Guidelines ...................................................................... 44 Power Dissipation and Standby Mode ..................................... 23 Outline Dimensions ....................................................................... 45 Noise Shaping Requantizer ........................................................... 24 Ordering Guide .......................................................................... 45 22% Bandwidth Mode (>40 MHz at 184.32 MSPS) .............. 24 Rev. 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