80 MHz Bandwidth, IF Receiver Data Sheet AD6677 FEATURES GENERAL DESCRIPTION JESD204B Subclass 0 or Subclass 1 coded serial digital outputs The AD6677 is an 11-bit, 250 MSPS, intermediate frequency Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and (IF) receiver specifically designed to support multi-antenna 250 MSPS with noise shaping requantizer (NSR) set to 33% systems in telecommunication applications where high dynamic Spurious-free dynamic range (SFDR) = 87 dBc at 185 MHz A IN range performance, low power, and small size are desired. and 250 MSPS The device consists of a high performance ADC and an NSR Total power consumption: 435 mW at 250 MSPS digital block. The ADC consists of a multistage, differential 1.8 V supply voltages pipelined architecture with integrated output error correction Integer 1 to 8 input clock divider logic, and each ADC features a wide bandwidth switched capacitor Sample rates of up to 250 MSPS sampling network within the first stage of the differential pipeline. IF sampling frequencies of up to 400 MHz An integrated voltage reference eases design considerations. A duty Internal analog-to-digital converter (ADC) voltage reference cycle stabilizer compensates for variations in the ADC clock duty Flexible analog input range cycle, allowing the converters to maintain excellent performance. 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) The ADC output is connected internally to an NSR block. The ADC clock duty cycle stabilizer (DCS) integrated NSR circuitry allows for improved SNR performance Serial port control in a smaller frequency band within the Nyquist bandwidth. Energy saving power-down modes The device supports two different output modes selectable via APPLICATIONS the serial port interface (SPI). With the NSR feature enabled, Communications the output of the ADC is processed such that the AD6677 Diversity radio and smart antenna multiple input, multiple supports enhanced SNR performance within a limited portion output (MIMO) systems of the Nyquist bandwidth while maintaining an 11-bit output Multimode digital receivers (3G) resolution. TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems General-purpose software radios FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND AD6677 JESD204B INTERFACE NOISE VIN+ SHAPING CML, TX PIPELINE SERDOUT0 REQUANTIZER OUTPUTS HIGH 11-BIT ADC (NSR) VIN SPEED SERIALIZERS VCM CMOS CONTROL DIGITAL PDWN REGISTERS INPUT SYSREF SYNCINB CLOCK CLK GENERATION RFCLK CMOS DIGITAL CMOS DIGITAL FAST FD OUTPUT INPUT/OUTPUT DETECT RST SDIO SCLK CS Figure 1. Rev. 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Technical Support www.analog.com 11411-001AD6677 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Noise Shaping Requantizer ........................................................... 23 Applications ....................................................................................... 1 22% Bandwidth Mode (>40 MHz at 184.32 MSPS) .............. 23 General Description ......................................................................... 1 33% Bandwidth Mode (>60 MHz at 184.32 MSPS) .............. 24 Functional Block Diagram .............................................................. 1 Digital Outputs ............................................................................... 25 Revision History ............................................................................... 2 JESD204B Transmit Top Level Description ............................ 25 Product Highlights ........................................................................... 3 ADC Overrange and Gain Control .......................................... 30 Specifications ..................................................................................... 4 DC Correction (DCC) ................................................................... 32 ADC DC Specifications ............................................................... 4 DC Correction Bandwidth ........................................................ 32 ADC AC Specifications ............................................................... 5 DC Correction Readback .......................................................... 32 Digital Specifications ................................................................... 6 DC Correction Freeze ................................................................ 32 Switching Specifications .............................................................. 8 DC Correction Enable Bits ....................................................... 32 Timing Specifications .................................................................. 9 Serial Port Interface (SPI) .............................................................. 33 Absolute Maximum Ratings .......................................................... 10 Configuration Using the SPI ..................................................... 33 Thermal Characteristics ............................................................ 10 Hardware Interface ..................................................................... 33 ESD Caution ................................................................................ 10 SPI Accessible Features .............................................................. 33 Pin Configuration and Function Descriptions ........................... 11 Memory Map .................................................................................. 35 Typical Performance Characteristics ........................................... 13 Reading the Memory Map Register Table ............................... 35 Equivalent Circuits ......................................................................... 16 Memory Map Register Table ..................................................... 36 Theory of Operation ...................................................................... 17 Memory Map Register Descriptions ........................................ 40 ADC Architecture ...................................................................... 17 Applications Information .............................................................. 44 Analog Input Considerations .................................................... 17 Design Guidelines ...................................................................... 44 Voltage Reference ....................................................................... 19 Outline Dimensions ....................................................................... 45 Clock Input Considerations ...................................................... 19 Ordering Guide .......................................................................... 45 Power Dissipation and Standby Mode ..................................... 22 REVISION HISTORY 3/14Rev. 0 to Rev. A 1/16Rev. B to Rev. C Changes to General Description Section ...................................... 3 Changes to Data Output Parameters, Table 4 ................................ 8 Changes to Nyquist Clock Input Section .................................... 19 Changes to Figure 3 ........................................................................... 9 Changes to JESD204B Overview Section .................................... 25 Changes to Figure 52 ...................................................................... 28 4/13Revision 0: Initial Version Change to Table 17 ......................................................................... 38 5/14Rev. A to Rev. B Change to RF Clock Rate Parameter, Table 3 ............................... 6 Change to Pin 11, Table 8 .............................................................. 11 Change to RF Clock Input Options Section................................ 20 Changes to Transfer Register Map Section ................................. 35 Changes to Table 17 ........................................................................ 37 Change to JESD204B Link Control 2 (Address 0x60) ............... 41 Rev. C Page 2 of 48