RF Diversity and 1.2 GHz Bandwidth Observation Receiver Data Sheet AD6688 FEATURES Two Integrated wideband digital processors per channel 48-bit NCO JESD204B (Subclass 1) coded serial digital outputs 4 cascaded half band filters Support for lane rates up to 16 Gbps per lane Phase coherent NCO switching 1.7 W total power per channel at 3 GSPS (default settings) Up to 4 channels available Performance at 2 dBFS amplitude, 2.6 GHz input Serial port control SFDR = 70 dBFS Integer clock divide by 2 and divide by 4 NSD = 148.0 dBFS/Hz Flexible JESD204B lane configurations Performance at 9 dBFS amplitude, 2.6 GHz input On-chip dither SFDR = 75 dBFS NSD = 151.4 dBFS/Hz APPLICATIONS Integrated input buffer Diversity multiband, multimode digital receivers Noise density = 152.0 dBFS/Hz 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A 0.975 V, 1.9 V, and 2.5 V dc supply operation DOCSIS 3.0 CMTS upstream receive paths 9 GHz analog input full power bandwidth (3 dB) HFC digital reverse path receivers Amplitude detect bits for efficient AGC implementation FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1 SR DVDD DRVDD1 DRVDD2 SPIVDD (0.975V) (1.9V) (2.5V) (0.975V) (0.975V) (1.9V) (1.9V) (0.975V) BUFFER SIGNAL PROCESSING VIN+A ADC VINA DIGITAL DOWN CONVERSION SERDOUT0 DIGITAL DOWN CONVERSION SERDOUT1 JESD204B SERDOUT2 FAST SIGNAL DATA DATA LINK 8 SERDOUT3 DETECT MONITOR ROUTER ROUTER AND DIGITAL DOWN CONVERSION MUX SERDOUT4 MUX TX SERDOUT5 OUTPUTS PDWN/ DIGITAL DOWN CONVERSION SERDOUT6 STBY SERDOUT7 BUFFER VIN+B ADC GPIO A0/GPIO A1 GPIO B0/GPIO B1 VINB SYNCINB NCO BAND SELECT VREF CLOCK FD A/GPIO A0 CLK+ DISTRIBUTION GPIO A1 JESD204B GPIO MUX SUBCLASS1 FD B/GPIO B0 AD6688 CLK SPI CONTROL 2 CONTROL GPIO B1 4 AGND SYSREF SDIO SCLK CSB DGND DRGND Figure 1. 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Technical Support www.analog.com PROGRAMMABLE FIR FILTER 15548-001AD6688 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Gain Stage ......................................................................... 59 Applications ....................................................................................... 1 DDC Complex to Real Conversion ......................................... 59 Functional Block Diagram .............................................................. 1 DDC Mixed Decimation Settings ............................................ 60 Revision History ............................................................................... 3 DDC Example Configurations ................................................. 62 General Description ......................................................................... 4 DDC Power Consumption ........................................................ 65 Product Highlights ........................................................................... 4 Signal Monitor ................................................................................ 66 Specifications ..................................................................................... 5 SPORT Over JESD204B ............................................................ 67 DC Specifications ......................................................................... 5 Digital Outputs ............................................................................... 69 AC Specifications .......................................................................... 7 Introduction to the JESD204B Interface ................................. 69 Digital Specifications ................................................................... 9 JESD204B Overview .................................................................. 69 Switching Specifications ............................................................ 10 Functional Overview ................................................................. 70 Timing Specifications ................................................................ 11 JESD204B Link Establishment ................................................. 70 Absolute Maximum Ratings .......................................................... 12 Physical Layer (Driver) Outputs .............................................. 72 Thermal Resistance .................................................................... 12 f 4 Mode ................................................................................... 72 S ESD Caution ................................................................................ 12 Setting Up the AD6688 Digital Interface ................................ 74 Pin Configuration and Function Descriptions ........................... 13 Deterministic Latency .................................................................... 79 Typical Performance Characteristics ........................................... 16 Subclass 0 Operation .................................................................. 79 Equivalent Circuits ......................................................................... 21 Subclass 1 Operation .................................................................. 79 Theory of Operation ...................................................................... 25 Multichip Synchronization ............................................................ 81 ADC Architecture ...................................................................... 25 Normal Mode .............................................................................. 81 Analog Input Considerations .................................................... 25 Timestamp Mode ....................................................................... 81 Voltage Reference ....................................................................... 29 SYSREF Input .............................................................................. 82 DC Offset Calibration ................................................................ 30 SYSREF Setup/Hold Window Monitor ................................. 85 Clock Input Considerations ...................................................... 30 Latency ............................................................................................. 87 Power-Down/Standby Mode..................................................... 32 End to End Total Latency .......................................................... 87 Temperature Diode .................................................................... 32 Example Latency Calculations.................................................. 87 ADC Overrange and Fast Detect .................................................. 34 LMFC-Referenced Latency ....................................................... 87 ADC Overrange .......................................................................... 34 Test Modes ....................................................................................... 89 Fast Threshold Detection (FD A and FD B) ........................ 34 ADC Test Modes ........................................................................ 89 ADC Application Modes and JESD204B Tx Converter JESD204B Block Test Modes .................................................... 90 Mapping ........................................................................................... 35 Serial Port Interface ........................................................................ 92 Programmable FIR Filters ............................................................. 37 Configuration Using the SPI ..................................................... 92 Supported Modes........................................................................ 37 Hardware Interface ..................................................................... 92 Programming Instructions ........................................................ 40 SPI Accessible Features .............................................................. 92 Digital Downconverter (DDC) ..................................................... 42 Memory Map .................................................................................. 93 DDC I/Q Input Selection .......................................................... 42 Reading the Memory Map Register Table ............................... 93 DDC I/Q Output Selection ....................................................... 42 Memory Map Register Details .................................................. 94 DDC General Description ........................................................ 42 Applications Information ............................................................ 136 DDC Frequency Translation ..................................................... 45 Power Supply Recommendations ........................................... 136 DDC Decimation Filters ............................................................ 53 Layout GuideLines ................................................................... 137 Rev. 0 Page 2 of 138