1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Data Sheet AD7262 FEATURES FUNCTIONAL BLOCK DIAGRAM AV V A CC REF Dual simultaneous sampling 12-bit, 2-channel analog-to- digital converter (ADC) REF BUF AD7262 True differential analog inputs Programmable gain stage: 1, 2, 3, 4, 6, 8, 12, 16, 12-BIT V + SUCCESSIVE A OUTPUT 24, 32, 48, 64, 96, 128 D A PGA T/H OUT APPROXIMATION DRIVERS V A ADC Throughput rate per ADC 1 MSPS for AD7262 SCLK 500 kSPS for AD7262-5 CAL CS Analog input impedance: >1 G CONTROL REFSEL LOGIC Wide input bandwidth G0 G1 3 dB bandwidth: 1.7 MHz at gain = 2 G2 G3 4 on-chip comparators V DRIVE SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32 12-BIT V + B Device offset calibration, system gain calibration SUCCESSIVE OUTPUT T/H D B PGA OUT APPROXIMATION DRIVERS V B On-chip reference: 2.5 V ADC PD0/D IN 40C to +105C operation PD1 BUF PD2 High speed serial interface V B REF SPI/QSPI/MICROWIRE/DSP compatible C C V A B CC 48-lead LFCSP and LQFP C + A OUTPUT C A OUT DRIVERS C A GENERAL DESCRIPTION COMP C + B OUTPUT C B OUT The AD7262/AD7262-5 are dual, 12-bit, high speed, low power, DRIVERS C B COMP C C GND A B successive approximation ADCs that operate from a single 5 V C C V C D CC power supply. The AD7262 features throughput rates of up to C + C OUTPUT C C 1 MSPS per on-chip ADC. The AD7262-5 features throughput OUT DRIVERS C C COMP rates of up to 500 kSPS. Two complete ADC functions allow C + D OUTPUT C D OUT DRIVERS C D simultaneous sampling and conversion of two channels. Each COMP C C GND C D ADC is preceded by a true differential analog input with a PGA. There are 14 gain settings available: 1, 2, 3, 4, 6, 8, 12, AGND DGND 16, 24, 32, 48, 64, 96, and 128. Figure 1. The AD7262/AD7262-5 contain four comparators. Comparator A and Comparator B are optimized for low power, while Compara- PRODUCT HIGHLIGHTS tor C and Comparator D have fast propagation delays. The 1. Integrated PGA with a variety of flexible gain settings to AD7262/AD7262-5 feature a calibration function to remove any allow detection and conversion of low level analog signals. device offset error and programmable gain adjust registers to allow 2. Each PGA is followed by a dual simultaneous sampling for input path (for example, sensor) offset and gain compensation. ADC, featuring throughput rates of 1 MSPS per ADC for The AD7262/AD7262-5 have an on-chip 2.5 V reference that the AD7262. The conversion results of both ADCs are can be disabled if an external reference is preferred. simultaneously available on separate data lines or in succes- The AD7262/AD7262-5 are ideally suited for monitoring small sion on one data line if only one serial port is available. amplitude signals from a variety of sensors. They include all the 3. Four integrated comparators that can be used to count functionality needed for monitoring the position feedback signals signals from pole sensors in motor control applications. from a variety of analog encoders used in motor control systems. 4. Internal 2.5 V reference. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com 07606-001AD7262 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Application Details ..................................................................... 20 General Description ......................................................................... 1 Modes of Operation ....................................................................... 22 Functional Block Diagram .............................................................. 1 Pin-Driven Mode ....................................................................... 22 Product Highlights ........................................................................... 1 Gain Selection ............................................................................. 22 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 22 Specifications ..................................................................................... 3 Control Register ......................................................................... 23 Timing Specifications .................................................................. 6 On-Chip Registers ...................................................................... 24 Timing Diagram ........................................................................... 6 Serial Interface ................................................................................ 25 Absolute Maximum Ratings ............................................................ 7 Calibration ....................................................................................... 27 ESD Caution .................................................................................. 7 Internal Offset Calibration ........................................................ 27 Pin Configurations and Function Descriptions ........................... 8 Adjusting the Offset Calibration Registers ................................. 28 Typical Performance Characteristics ........................................... 10 System Gain Calibration............................................................ 28 Terminology .................................................................................... 14 Microprocessor Interfacing ........................................................... 29 Theory of Operation ...................................................................... 15 AD7262/AD7262-5 to ADSP-BF531 ....................................... 29 Circuit Information .................................................................... 15 Application Hints ........................................................................... 30 Comparators ................................................................................ 15 Grounding and Layout .............................................................. 30 Operation ..................................................................................... 15 PCB Design Guidelines for LFCSP .......................................... 30 Analog Inputs .............................................................................. 15 Outline Dimensions ....................................................................... 31 VDRIVE ............................................................................................ 16 Ordering Guide .......................................................................... 31 Reference ..................................................................................... 17 Typical Connection Diagrams .................................................. 17 REVISION HISTORY 8/2015Rev. 0 to Rev. A 1/2018Rev. B to Rev. C Changed ADSP-BF53x to ADSP-BF531 ..................... Throughout Changed CP-48-4 to CP-48-1 ...................................... Throughout Changes to Table 4 ............................................................................. 9 Updated Outline Dimensions ....................................................... 31 Change to Serial Interface Section ............................................... 25 Changes to Ordering Guide .......................................................... 31 Changes to Figure 34 and Figure 34 Caption ............................. 26 Change to Microprocessor Interfacing Section and Figure 37 . 29 11/2016Rev. A to Rev. B Changes to AD7262/AD7262-5 to ADSP-BF531 Section......... 29 Change to Figure 4 ........................................................................... 8 Updated Outline Dimensions ....................................................... 31 Change to Pin 31, 32 Description, Table 4 .................................... 9 Changes to Serial Interface Section .............................................. 25 7/2008Revision 0: Initial Version Changes to Figure 34 and Figure 34 Caption ............................. 26 Updated Outline Dimensions ....................................................... 31 Changes to Ordering Guide .......................................................... 31 Rev. C Page 2 of 32