Differential/Single-Ended Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC AD7266 FEATURES FUNCTIONAL BLOCK DIAGRAM REF SELECT D A AV DV CAP DD DD Dual 12-bit, 3-channel ADC Throughput rate: 2 MSPS REF BUF Specified for V of 2.7 V to 5.25 V DD AD7266 Power consumption V A1 9 mW at 1.5 MSPS with 3 V supplies V A2 27 mW at 2 MSPS with 5 V supplies 12-BIT V A3 SUCCESSIVE OUTPUT MUX T/H D A Pin-configurable analog inputs OUT APPROXIMATION DRIVERS V A4 ADC 12-channel single-ended inputs V A5 SCLK 6-channel fully differential inputs V A6 CS 6-channel pseudo differential inputs RANGE SGL/DIFF 70 dB SNR at 50 kHz input frequency CONTROL LOGIC A0 Accurate on-chip reference: 2.5 V A1 A2 0.2% maximum 25C, 20 ppm/C maximum V B1 V Dual conversion with read 437.5 ns, 32 MHz SCLK B2 V DRIVE High speed serial interface V B3 MUX 12-BIT V B4 SUCCESSIVE OUTPUT SPI-/QSPI-/MICROWIRE-/DSP-compatible D B T/H OUT APPROXIMATION DRIVERS V ADC 40C to +125C operation B5 V B6 Shutdown mode: 1 A maximum BUF 32-lead LFCSP and 32-lead TQFP 1 MSPS version, AD7265 AGND AGND AGND D B DGND DGND CAP GENERAL DESCRIPTION Figure 1. 1 The AD7266 is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V The AD7266 is available in a 32-lead LFCSP and a power supply and features throughput rates up to 2 MSPS. The 32-lead TQFP. device contains two ADCs, each preceded by a 3-channel PRODUCT HIGHLIGHTS multiplexer, and a low noise, wide bandwidth track-and-hold 1. Two Complete ADC Functions Allow Simultaneous amplifier that can handle input frequencies in excess of 30 MHz. Sampling and Conversion of Two Channels. The conversion process and data acquisition use standard Each ADC has three fully/pseudo differential pairs, or six control inputs allowing easy interfacing to microprocessors or single-ended channels, as programmed. The conversion CS DSPs. The input signal is sampled on the falling edge of result of both channels is simultaneously available on conversion is also initiated at this point. The conversion time is separate data lines, or in succession on one data line if only determined by the SCLK frequency. There are no pipelined one serial port is available. delays associated with the part. 2. High Throughput with Low Power Consumption. The AD7266 uses advanced design techniques to achieve very The AD7266 offers a 1.5 MSPS throughput rate with low power dissipation at high throughput rates. With 5 V 11.4 mW maximum power dissipation when operating at 3 V. supplies and a 2 MSPS throughput rate, the part consumes 3. The AD7266 offers both a standard 0 V to VREF input range 6.2 mA maximum. The part also offers flexible power/ and a 2 VREF input range. throughput rate management when operating in normal mode 4. No Pipeline Delay. as the quiescent current consumption is so low. The part features two standard successive approximation The analog input range for the part can be selected to be a 0 V ADCs with accurate control of the sampling instant via a to V (or 2 V ) range, with either straight binary or twos REF REF CS input and once off conversion control. complement output coding. The AD7266 has an on-chip 2.5 V 1 Protected by U.S. Patent No. 6,681,332 reference that can be overdriven when an external reference is preferred. This external reference range is 100 mV to VDD. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 www.analog.com No license is granted by implication or otherwise under any patent or patent rights of Analog Fax: 781.461.3113 20052020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. 04603-001AD7266 TABLE OF CONTENTS Features .............................................................................................. 1 VDRIVE ............................................................................................ 18 General Description ......................................................................... 1 Modes of Operation ....................................................................... 19 Functional Block Diagram .............................................................. 1 Normal Mode ............................................................................. 19 Product Highlights ........................................................................... 1 Partial Power-Down Mode ....................................................... 19 Revision History ............................................................................... 2 Full Power-Down Mode ............................................................ 20 Specifications .................................................................................... 3 Power-Up Times ........................................................................ 21 Timing Specifications .................................................................. 5 Power vs. Throughput Rate ...................................................... 21 Absolute Maximum Ratings ........................................................... 6 Serial Interface ................................................................................ 22 ESD Caution.................................................................................. 6 Microprocessor Interfacing .......................................................... 23 Pin Configuration and Function Descriptions ............................ 7 AD7266 to ADSP-218x ............................................................. 23 Typical Performance Characteristics ............................................. 9 AD7266 to ADSP-BF53x ........................................................... 24 Terminology .................................................................................... 11 AD7266 to TMS320C541 .......................................................... 24 Theory of Operation ...................................................................... 13 AD7266 to DSP563xx ................................................................ 25 Circuit Information ................................................................... 13 Application Hints ........................................................................... 26 Converter Operation .................................................................. 13 Grounding and Layout .............................................................. 26 Analog Input Structure .............................................................. 13 PCB Design Guidelines for LFCSP .......................................... 26 Analog Inputs ............................................................................. 14 Evaluating the AD7266 Performance ...................................... 26 Analog Input Selection .............................................................. 17 Outline Dimensions ....................................................................... 27 Output Coding ............................................................................ 17 Ordering Guide .......................................................................... 27 Transfer Functions ..................................................................... 18 Digital Inputs .............................................................................. 18 REVISION HISTORY 11/2020Rev. B to Rev. C 11/2006Rev. 0 to Rev. A Changed CP-32-2 to CP-32-7 ...................................... Throughout Changes to Format ............................................................. Universal Changes to Figure 2 .......................................................................... 7 Changes to Reference Input/Output Section ................................ 4 Updated Outline Dimensions ....................................................... 27 Changes to Table 4 ............................................................................ 7 Changes to Ordering Guide .......................................................... 27 Changes to Terminology Section ................................................. 11 Changes to Figure 24 and Differential Mode Section ............... 15 Changes to Figure 29 ..................................................................... 16 5/2011Rev. A to Rev. B Changes to Figure 39 ..................................................................... 21 Changes to Mnemonic Order for Pin 13 to Pin 18, Pin 23 to Changes to AD7265 to ADSP-BF53x Section ............................ 24 Pin 25, and Pin 28, Pin 30 in Table 4 ............................................. 7 Updated Outline Dimensions ...................................................... 27 Added EPAD Note ........................................................................... 7 Changes to Ordering Guide .......................................................... 27 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 4/2005Revision 0: Initial Version Rev. C Page 2 of 28