3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT Data Sheet AD7276/AD7277/AD7278 FEATURES FUNCTIONAL BLOCK DIAGRAM V DD Throughput rate: 3 MSPS Specified for V of 2.35 V to 3.6 V DD Power consumption 12.6 mW at 3 MSPS with 3 V supplies 12-/10-/8-BIT SUCCESSIVE Wide input bandwidth V T/H IN APPROXIMATION ADC 70 dB SNR at 1 MHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI-/QSPI-/MICROWIRE-/DSP compatible SCLK Temperature range: 40C to +125C AD7276/ CONTROL SDATA AD7277/ LOGIC Power-down mode: 0.1 A typical AD7278 CS 6-lead TSOT package 8-lead MSOP package AD7476 and AD7476A pin compatible GND Figure 1. GENERAL DESCRIPTION Table 1. The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed, low power, successive approximation analog-to-digital converters Part Number Resolution Package (ADCs), respectively. The parts operate from a single 2.35 V AD7276 12 8-Lead MSOP 6-Lead TSOT to 3.6 V power supply and feature throughput rates of up to AD7277 10 8-Lead MSOP 6-Lead TSOT 3 MSPS. The parts contain a low noise, wide bandwidth track- AD7278 8 8-Lead MSOP 6-Lead TSOT 1 and-hold amplifier that can handle input frequencies in excess AD7274 12 8-Lead MSOP 8-Lead TSOT 1 of 55 MHz. AD7273 10 8-Lead MSOP 8-Lead TSOT The conversion process and data acquisition are controlled 1 Part contains external reference pin. using CS and the serial clock, allowing the devices to interface PRODUCT HIGHLIGHTS with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is initiated at this 1. 3 MSPS ADCs in a 6-lead TSOT package. point. There are no pipeline delays associated with the part. 2. AD7476/AD7477/AD7478 and AD7476A/AD7477A/ AD7478A pin compatible. The AD7276/AD7277/AD7278 use advanced design techniques 3. High throughput with low power consumption. to achieve very low power dissipation at high throughput rates. 4. Flexible power/serial clock speed management. This allows The reference for the part is taken internally from VDD. This maximum power efficiency at low throughput rates. allows the widest dynamic input range to the ADC therefore, 5. Reference derived from the power supply. the analog input range for the part is 0 to VDD. The conversion 6. No pipeline delay. The parts feature a standard successive rate is determined by the SCLK. approximation ADC with accurate control of the sampling instant via a input and once-off conversion control. CS Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. 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Trademarks and registered trademarks are the property of their respective owners. 04903-001AD7276/AD7277/AD7278 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 General Description ......................................................................... 1 Circuit Information ................................................................... 16 Functional Block Diagram .............................................................. 1 Converter Operation ................................................................. 16 Product Highlights ........................................................................... 1 ADC Transfer Function ............................................................ 16 Revision History ............................................................................... 2 Typical Connection Diagram ................................................... 16 Specifications .................................................................................... 3 Modes of Operation ................................................................... 18 AD7276 Specifications ................................................................. 3 Power vs. Throughput Rate ...................................................... 21 AD7277 Specifications ................................................................. 5 Serial Interface ................................................................................ 22 AD7278 Specifications ................................................................. 7 AD7278 in a 10 SCLK Cycle Serial Interface ......................... 24 Timing SpecificationsAD7276/AD7277/AD7278 ............... 8 Microprocessor Interfacing ...................................................... 24 Timing Examples ........................................................................ 10 Application Hints ........................................................................... 25 Absolute Maximum Ratings ......................................................... 11 Grounding and Layout .............................................................. 25 ESD Caution................................................................................ 11 Evaluating Performance ............................................................. 25 Pin Configurations and Function Descriptions ......................... 12 Outline Dimensions ....................................................................... 26 Performance Characteristics ......................................................... 13 Ordering Guide .......................................................................... 27 Terminology .................................................................................... 15 REVISION HISTORY 7/2020Rev. D to Rev. E 11/2009Rev. A to Rev. B Changes to Table 2 ............................................................................ 3 Change to Table 3 ............................................................................. 5 Changes to Table 3 ............................................................................ 5 7/2015Rev. C to Rev. D Changes to Table 4 ............................................................................ 7 Changes to Differential Nonlinearity Parameter, Table 2 .......... 3 Changes to Ordering Guide .......................................................... 27 Changes to Typical Connection Diagram Section ..................... 16 Changes to AD7276/AD7277/AD7278 to Blackfin Processor 10/2005Rev. 0 to Rev. A Section and Figure 36 ..................................................................... 24 Updated Format ................................................................. Universal Changes to Ordering Guide .......................................................... 27 Changes to Table 2 ............................................................................ 3 Changes to Table 5 ............................................................................ 8 5/2011Rev. B to Rev. C Changes to the Partial Power-Down Mode Section .................. 18 Changes to Figure 21 ..................................................................... 16 Changes to the Power vs. Throughput Rate Section ................. 21 Changes to Ordering Guide .......................................................... 27 Updated Outline Dimensions ...................................................... 26 Changes to Endnote 5 .................................................................... 27 Changes to Ordering Guide .......................................................... 26 7/2005Revision 0: Initial Version Rev. E Page 2 of 28