Differential Input, 1 MSPS a 12-Bit ADC in SOIC-8 and SO-8 AD7450 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast Throughput Rate: 1 MSPS V DD Specified for V of 3 V and 5 V DD Low Power at Max Throughput Rate: 3.75 mW Max at 833 kSPS with 3 V Supplies 9 mW Max at 1 MSPS with 5 V Supplies V IN+ Fully Differential Analog Input T/H 12-BIT SUCCESSIVE Wide Input Bandwidth: APPROXIMATION V IN ADC 70 dB SINAD at 300 kHz Input Frequency Flexible Power/Serial Clock Speed Management V REF No Pipeline Delays TM TM High-Speed Serial InterfaceSPI /QSPI TM MICROWIRE /DSP Compatible SCLK Power-Down Mode: 1 A Max AD7450 CONTROL SDATA LOGIC 8-Lead SOIC and SOIC Packages CS APPLICATIONS Transducer Interface GND Battery-Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications GENERAL DESCRIPTION The AD7450 is a 12-bit, high-speed, low power, successive The AD7450 uses advanced design techniques to achieve low approximation (SAR) analog-to-digital converter that features a power dissipation at high throughput rates. fully differential analog input. It operates from a single 3 V or 5 V power supply and features throughput rates up to 833 kSPS or PRODUCT HIGHLIGHTS 1 MSPS, respectively. 1. Operation with either 3 V or 5 V power supplies. This part contains a low noise, wide bandwidth, differential track- 2. High throughput with low power consumption. With a 3 V and-hold amplifier (T/H) that can handle input frequencies in supply, the AD7450 offers 3.75 mW max power consumption excess of 1 MHz with the 3 dB point typically being 20 MHz. for 833 kSPS throughput. The reference voltage for the AD7450 is applied externally to the 3. Fully differential analog input. V pin and can be varied from 100 mV to 3.5 V, depending REF 4. Flexible power/serial clock speed management. The conversion on the power supply and what suits the application. The value of rate is determined by the serial clock, allowing the power the reference voltage determines the common-mode voltage to be reduced as the conversion time is reduced through range of the part. With this truly differential input structure and the serial clock speed increase. This part also features a variable reference input, the user can select a variety of input shutdown mode to maximize power efficiency at lower ranges and bias points. throughput rates. The conversion and data acquisition processes are controlled 5. Variable voltage reference input. using CS and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signals are sampled 6. No pipeline delay. on the falling edge of CS, and the conversion is also initiated at 7. Accurate control of the sampling instant via a CS input and this point. once-off conversion control. The SAR architecture of this part ensures that there are no 8. ENOB > 8 bits typically with 100 mV reference. pipeline delays. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax: 781/461/3113 Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices.1 AD7450SPECIFICATIONS (V = 2.7 V to 3.3 V, f = 15 MHz, f = 833 kSPS, V = 1.25 V, F = 200 kHz DD SCLK S REF IN 2 V = 4.75 V to 5.25 V, f = 18 MHz, f = 1 MSPS, V = 2.5 V, F = 300 kHz V = V T = T to T , unless otherwise noted.) DD SCLK S REF IN CM REF A MIN MAX Parameter Conditions/Comments A Version B Version Unit DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) Ratio V = 5 V 70 70 dB min DD 3 (SINAD) V = 3 V 68 68 dB min DD 3 Total Harmonic Distortion (THD) V = 5 V, 80 dB typ 75 75 dB max DD V = 3 V, 78 dB typ 73 73 dB max DD 3 Peak Harmonic or Spurious Noise V = 5 V, 82 dB typ 75 75 dB max DD V = 3 V, 80 dB typ 73 73 dB max DD 3 Intermodulation Distortion (IMD) Second Order Terms 85 85 dB typ Third Order Terms 85 85 dB typ 3 Aperture Delay 10 10 ns typ 3 Aperture Jitter 50 50 ps typ 3 Full Power Bandwidth 3 dB 20 20 MHz typ 0.1 dB 2.5 2.5 MHz typ Power Supply Rejection Ratio 3, 4 (PSRR) 87 87 dB typ DC ACCURACY Resolution 12 12 Bits 3 Integral Nonlinearity (INL) 2 1 LSB max 3 Differential Nonlinearity (DNL) Guaranteed No Missed Codes to 12 Bits 1/+2 1 LSB max 3 Zero Code Error V = 5 V 3 3 LSB max DD V = 3 V 6 6 LSB max DD 3 Positive Gain Error V = 5 V 3 3 LSB max DD V = 3 V 6 6 LSB max DD 3 Negative Gain Error V = 5 V 3 3 LSB max DD V = 3 V 6 6 LSB max DD ANALOG INPUT 5 Full-Scale Input Span 2 V V V V V V REF IN+ IN IN+ IN Absolute Input Voltage 2 V V = V V V /2 V V /2 V IN+ CM REF CM REF CM REF 2 V V = V V V /2 V V /2 V IN CM REF CM REF CM REF DC Leakage Current 1 1 A max Input Capacitance When in Track 20 20 pF typ When in Hold 6 6 pF typ REFERENCE INPUT V Input Voltage 5 V supply (1% tolerance for REF 6 6 specified performance) 2.5 2.5 V 3 V supply (1% tolerance for 7 7 specified performance) 1.25 1.25 V DC Leakage Current 1 1 A max V Input Capacitance 15 15 pF typ REF LOGIC INPUTS Input High Voltage, V 2.4 2.4 V min INH Input Low Voltage, V 0.8 0.8 V max INL Input Current, I Typically 10 nA, V = 0 V or V 1 1 A max IN IN DD 8 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V V = 5 V, I = 200 A 2.8 2.8 V min OH DD SOURCE V = 3 V, I = 200 A 2.4 2.4 V min DD SOURCE Output Low Voltage, V I = 200 A 0.4 0.4 V max OL SINK Floating-State Leakage Current 1 1 A max 8 Floating-State Output Capacitance 10 10 pF max Output Coding Twos Twos Complement Complement 2 Rev. A