Pseudo Differential, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23 AD7453 FUNCTIONAL BLOCK DIAGRAM FEATURES V Specified for VDD of 2.7 V to 5.25 V DD Low power at max throughput rate: 3.3 mW max at 555 kSPS with V = 3 V DD 7.25 mW max at 555 kSPS with VDD = 5 V V Pseudo differential analog input IN+ 12-BIT T/H SUCCESSIVE Wide input bandwidth: V APPROXIMATION IN ADC 70 dB SINAD at 100 kHz input frequency V REF Flexible power/serial clock speed management No pipeline delays High speed serial interface: SCLK SPI/QSPI/MICROWIRE/DSP compatible SDATA Power-down mode: 1 A max AD7453 CONTROL LOGIC CS 8-lead SOT-23 package APPLICATIONS Transducer interface GND Battery-powered systems Figure 1. Data acquisition systems Portable instrumentation PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. Operation with 2.7 V to 5.25 V Power Supplies. 1 The AD7453 is a 12-bit, high speed, low power, successive 2. High Throughput with Low Power Consumption. With a approximation (SAR) analog-to-digital converter that features a 3 V supply, the AD7453 offers 3.3 mW max power pseudo differential analog input. This part operates from a consumption for a 555 kSPS throughput rate. single 2.7 V to 5.25 V power supply and features throughput 3. Pseudo Differential Analog Input. rates up to 555 kSPS. 4. Flexible Power/Serial Clock Speed Management. The The part contains a low noise, wide bandwidth, differential conversion rate is determined by the serial clock, allowing track-and-hold amplifier (T/H) that can handle input frequen- the power to be reduced as the conversion time is reduced cies up to 3.5 MHz. The reference voltage for the AD7453 is through the serial clock speed increase. This part also applied externally to the V pin and can range from 100 mV to REF features a shutdown mode to maximize power efficiency at VDD, depending on the power supply and what suits the lower throughput rates. application. 5. Variable Voltage Reference Input. The conversion process and data acquisition are controlled 6. No Pipeline Delay. CS using and the serial clock, allowing the device to interface CS 7. Accurate control of the sampling instant via a input and with microprocessors or DSPs. The input signals are sampled on once-off conversion control. CS the falling edge of the conversion is also initiated at this 8. ENOB > 10 bits Typically with 500 mV Reference. point. The SAR architecture of this part ensures that there are no 1 Protected by U.S. Patent Number 6,681,332. pipeline delays. The AD7453 uses advanced design techniques to achieve very low power dissipation. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. 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All rights reserved. 03155-A-001AD7453 TABLE OF CONTENTS Specifications..................................................................................... 3 Reference ..................................................................................... 13 Timing Specifications .................................................................. 5 Serial Interface ............................................................................ 13 Absolute Maximum Ratings............................................................ 6 Modes of Operation ....................................................................... 15 ESD Caution.................................................................................. 6 Normal Mode.............................................................................. 15 Pin Configuration and Function Descriptions............................. 7 Power-Down Mode.................................................................... 15 Terminology ...................................................................................... 8 Power-Up Time .......................................................................... 16 AD7453Typical Performance Characteristics ............................ 9 Power vs. Throughput Rate....................................................... 17 Circuit Information........................................................................ 11 Microprocessor and DSP Interfacing ...................................... 17 Converter Operation.................................................................. 11 Application Hints ....................................................................... 19 ADC Transfer Function............................................................. 11 Evaluating the AD7453s Performance .................................... 19 Typical Connection Diagram ................................................... 12 Outline Dimensions ....................................................................... 20 The Analog Input........................................................................ 12 Ordering Guide .......................................................................... 20 Digital Inputs .............................................................................. 13 REVISION HISTORY 2/04Data Sheet changed from Rev. A to Rev. B Added Patent Note ....................................................................... 1 1/04Data Sheet changed from Rev. 0 to Rev. A Updated Format..............................................................Universal Changes to General Description ................................................ 1 Changes to Specifications............................................................ 3 Changes to Timing Specifications.............................................. 5 Changes to Table 4........................................................................ 7 Replaced Figures 11, 12, 13........................................................ 10 Changes to Typical Connection Diagram section ................. 12 Change to Figure 18 ................................................................... 12 Changes to Reference Section................................................... 13 Changes to Timing Example 1.................................................. 14 8/03Rev. 0: Initial Version Rev. B Page 2 of 20