2 LC MOS a 5 ms 8-Bit ADC with Track/Hold AD7575 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast Conversion Time: 5 ms V On-Chip Track/Hold DD Low Total Unadjusted Error: 1 LSB TRACK Full Power Signal Bandwidth: 50 kHz AD7575 AIN AND HOLD Single +5 V Supply COMP 100 ns Data Access Time AGND Low Power (15 mW typ) DAC V REF Low Cost Standard 18-Lead DlPs or 20-Terminal CLOCK Surface Mount Packages CLK SAR OSCILLATOR DB7 CS LATCH AND CONTROL THREE STATE RD LOGIC OUTPUT DRIVERS TP DB0 GENERAL DESCRIPTION BUSY DGND The AD7575 is a high speed 8-bit ADC with a built-in track/ hold function. The successive approximation conversion tech- PRODUCT HIGHLIGHTS nique is used to achieve a fast conversion time of 5 m s, while the 1. Fast Conversion Time/Low Power built-in track/hold allows full-scale signals up to 50 kHz (386 mV/m s The fast, 5 m s, conversion time of the AD7575 makes it slew rate) to be digitized. The AD7575 requires only a single +5 V suitable for digitizing wideband signals at audio and ultra- supply and a low cost, 1.23 V bandgap reference in order to convert sonic frequencies while retaining the advantage of low an input signal range of 0 to 2 V . REF CMOS power consumption. The AD7575 is designed for easy interfacing to all popular 8-bit 2. On-Chip Track/Hold microprocessors using standard microprocessor control signals The on-chip track/hold function is completely self-contained (CS and RD) to control starting of the conversion and reading of and requires no external hold capacitor. Signals with slew the data. The interface logic allows the AD7575 to be easily rates up to 386 mV/m s (e.g., 2.46 V peak-to-peak 50 kHz sine configured as a memory mapped device, and the part can be waves) can be digitized with full accuracy. interfaced as SLOW-MEMORY or ROM. All data outputs of 3. Low Total Unadjusted Error the AD7575 are latched and three-state buffered to allow direct The zero, full-scale and linearity errors of the AD7575 are so connection to a microprocessor data bus or I/O port. low that the total unadjusted error at any point on the trans- The AD7575 is fabricated in an advanced, all ion-implanted high fer function is less than 1 LSB, and offset and gain adjust- 2 speed Linear Compatible CMOS (LC MOS) process and is ments are not required. available in a small, 0.3 wide, 18-lead DIP, 18-lead SOIC or in 4. Single Supply Operation other 20-terminal surface mount packages. Operation from a single +5 V supply with a low cost +1.23 V bandgap reference allows the AD7575 to be used in 5 V microprocessor systems without any additional power supplies. 5. Fast Digital Interface Fast interface timing allows the AD7575 to interface easily to the fast versions of most popular microprocessors such as the Z80H, 8085A-2, 6502B, 68B09 and the DSP processor, the TMS32010. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: (V = +5 V, V = +1.23 V, AGND = DGND = 0 V f = 4 MHz external DD REF CLK AD7575SPECIFICATIONS all specifications T to T unless otherwise noted) MIN MAX 1 Parameter J, A Versions K, B Versions S Version T Version Units Conditions/Comments ACCURACY Resolution 8 8 8 8 Bits Total Unadjusted Error 2 1 2 1 LSB max Relative Accuracy 1 1/2 1 1/2 LSB max Minimum Resolution for Which No Missing Codes Is Guaranteed 8 8 8 8 Bits max Full-Scale Error +25 C 1 1 1 1 LSB max Full-Scale TC Is Typically 5 ppm/ C T to T 1 1 1 1 LSB max MIN MAX 2 Offset Error +25 C 1/2 1/2 1/2 1/2 LSB max Offset TC Is Typically 5 ppm/ C T to T 1/2 1/2 1/2 1/2 LSB max MIN MAX ANALOG INPUT Voltage Range 0 to 2 V 0 to 2 V 0 to 2 V 0 to 2 V Volts 1 LSB = 2 V /256 See Figure 16 REF REF REF REF REF DC Input Impedance 10 10 10 10 MW min Slew Rate, Tracking 0.386 0.386 0.386 0.386 V/m s max 3 SNR 45 45 45 45 dB min V = 2.46 V p-p 10 kHz See Figure 11 IN REFERENCE INPUT V (For Specified Performance) 1.23 1.23 1.23 1.23 Volts 5% REF I 500 500 500 500 m A max REF LOGIC INPUTS CS, RD V , Input Low Voltage 0.8 0.8 0.8 0.8 V max INL V , Input High Voltage 2.4 2.4 2.4 2.4 V min INH I , Input Current IN +25 C 1 1 1 1 m A max V = 0 or V IN DD T to T 10 10 10 10 m A max V = 0 or V MIN MAX IN DD 3 C , Input Capacitance 10 10 10 10 pF max IN CLK V , Input Low Voltage 0.8 0.8 0.8 0.8 V max lNL V , Input High Voltage 2.4 2.4 2.4 2.4 V min INH I , Input Low Current 700 700 800 800 m A max V = 0 V INL INL I , Input High Current 700 700 800 800 m A max V = V INH INH DD LOGIC OUTPUTS BUSY, DB0 to DB7 V , Output Low Voltage 0.4 0.4 0.4 0.4 V max I = 1.6 mA OL SINK V , Output High Voltage 4.0 4.0 4.0 4.0 V min I = 40 m A OH SOURCE DB0 to DB7 Floating State Leakage Current 1 1 10 10 m A max V = 0 to V OUT DD 3 Floating State Output Capacitance 10 10 10 10 pF max 4 CONVERSION TIME With External Clock 5 5 5 5 msf = 4 MHz CLK With Internal Clock, T = +25 C5 5 5 5 m s min Using Recommended Clock A 15 15 15 15 m s max Components Shown in Figure 15 5 POWER REQUIREMENTS V +5 +5 +5 +5 Volts 5% for Specified Performance DD I 6 6 7 7 mA max Typically 3 mA with V = +5 V DD DD Power Dissipation 15 15 15 15 mW typ Power Supply Rejection 1/4 1/4 1/4 1/4 LSB max 4.75 V V 5.25 V DD NOTES 1 Temperature ranges are as follows: J, K Versions 0 C to +70 C A, B Versions 25 C to +85 C S, T Versions 55 C to +125 C 2 Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB. 3 Sample tested at +25 C to ensure compliance. 4 Accuracy may degrade at conversion times other than those specified. 5 Power supply current is measured when AD7575 is inactive i.e., when CS = RD = BUSY = logic HIGH. Specifications subject to change without notice. 2 REV. B