8-/10-Channel, Low Voltage, a Low Power, - ADCs AD7708/AD7718 FEATURES GENERAL DESCRIPTION 8-/10-Channel, High Resolution - ADCs The AD7708/AD7718 are complete analog front-ends for low AD7708 Has 16-Bit Resolution frequency measurement applications. The AD7718 contains a AD7718 Has 24-Bit Resolution 24-bit - ADC with PGA and can be configured as 4/5 fully- Factory-Calibrated differential input channels or 8/10 pseudo-differential input Single Conversion Cycle Setting channels. Two pins on the device are configurable as analog Programmable Gain Front End inputs or reference inputs. The AD7708 is a 16-bit version of Simultaneous 50 Hz and 60 Hz Rejection the AD7718. Input signal ranges from 20 mV to 2.56 V can be VREF Select Allows Absolute and Ratiometric directly converted using these ADCs. Signals can be converted Measurement Capability directly from a transducer without the need for signal conditioning. Operation Can Be Optimized for The device operates from a 32 kHz crystal with an on-board PLL Analog Performance (CHOP = 0) or generating the required internal operating frequency. The output Channel Throughput (CHOP = 1) data rate from the part is software programmable. The peak-to- INTERFACE peak resolution from the part varies with the programmed gain 3-Wire Serial and output data rate. TM TM TM SPI , QSPI , MICROWIRE , and DSP-Compatible The part operates from a single 3 V or 5 V supply. When operating Schmitt Trigger on SCLK from 3 V supplies, the power dissipation for the part is 3.84 mW typ. Both parts are pin-for-pin compatible allowing an upgradable POWER path from 16 to 24 bits without the need for hardware modifica- Specified for Single 3 V and 5 V Operation tions. The AD7708/AD7718 are housed in 28-lead SOIC and Normal: 1.28 mA Typ 3 V TSSOP packages. Power-Down: 30 A (32 kHz Crystal Running) On-Chip Functions Rail-to-Rail Input Buffer and PGA 2-Bit Digital I/O Port APPLICATIONS Industrial Process Control Instrumentation Pressure Transducers Portable Instrumentation Smart Transmitters FUNCTIONAL BLOCK DIAGRAM DVDD DGND REFIN2(+)/AIN9 REFIN1(+) REFIN2()/AIN10 REFIN1() XTAL1 XTAL2 OSC AND PLL AIN1 AIN2 POS BUF AIN3 AIN4 DOUT REFIN(+) REFIN() AIN5 SERIAL DIN PGA MUX NEG BUF - ADC* INTERFACE AIN6 SCLK AND AIN7 CS *AD7708 16-BIT ADC CONTROL AIN8 RDY *AD7718 24-BIT ADC LOGIC RESET AVDD AINCOM AD7708/AD7718 I/O PORT AVDD AGND P2 P1 SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. VREF Select is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 Analog Devices, Inc., 2001AD7708/AD7718 TABLE OF CONTENTS FEATURES . 1 User Nonprogrammable Test Registers 31 FUNCTIONAL BLOCK DIAGRAM . 1 Configuring the AD7708/AD7718 32 GENERAL DESCRIPTION . 1 DIGITAL INTERFACE . 34 AD7718 SPECIFICATIONS 3 MICROCOMPUTER/MICROPROCESSOR INTERFACING . 34 AD7708 SPECIFICATIONS 6 AD7708/AD7718 to 68HC11 Interface 34 TIMING CHARACTERISTICS . 9 AD7708/AD7718-to-8051 Interface 35 ABSOLUTE MAXIMUM RATINGS 10 AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface . 36 ORDERING GUIDE . 10 BASIC CONFIGURATION 36 PIN FUNCTION DESCRIPTIONS . 12 Analog Input Channels 37 PIN CONFIGURATION 13 Single-Ended Operation . 37 ADC CIRCUIT INFORMATION . 15 Chop Mode of Operation (CHOP = 0) 37 Signal Chain Overview (CHOP Enabled, CHOP = 0) . 15 Nonchop Mode of Operation (CHOP = 1) . 38 ADC NOISE PERFORMANCE CHOP ENABLED (CHOP = 0) . 17 Programmable Gain Amplifier . 38 Signal Chain Overview (CHOP Disabled CHOP = 1) . 19 Bipolar/Unipolar Configuration 38 ADC NOISE PERFORMANCE CHOP DISABLED Data Output Coding 38 (CHOP = 1) . 20 Oscillator Circuit . 39 ON-CHIP REGISTERS . 22 Reference Input 39 Communications Register 25 RESET Input . 39 Status Register . 26 Power-Down Mode . 39 Mode Register . 27 Calibration 40 Operating Characteristics when Addressing the Grounding and Layout 40 Mode and Control Registers . 28 APPLICATIONS 41 ADC Control Register . 28 Data Acquisition . 41 Filter Register . 29 Programmable Logic Controllers . 41 I/O Control Register 30 Converting Single-Ended Inputs . 42 ADC Data Result Register 30 Combined Ratiometric and Absolute Value Unipolar Mode 30 Measurement System 42 Bipolar Mode 31 Optimizing Throughput while Maximizing 50 Hz ADC Offset Calibration Coefficient Registers . 31 and 60 Hz Rejection in a Multiplexed Data Acquisition System 43 ADC Gain Calibration Coefficient Register . 31 OUTLINE DIMENSIONS . 44 ID Register (ID) . 31 2 REV. 0