AD7716BPZ Analog Devices

2 LC MOS a 22-Bit Data Acquisition System AD7716 FUNCTIONAL BLOCK DIAGRAM FEATURES 22-Bit Sigma-Delta ADC AV DV AV RESET A0 A1 A2 CLKIN CLKOUT DD DD SS Dynamic Range of 105 dB (146 Hz Input) 60.003% Integral Nonlinearity AD7716 On-Chip Low-Pass Digital Filter CLOCK GENERATION LOW PASS Cutoff Programmable from 584 Hz to 36.5 Hz ANALOG A 1 DIGITAL IN MODULATOR Linear Phase Response MODE FILTER CONTROL CASCIN Five Line Serial I/O LOGIC CASCOUT Twos Complement Coding LOW PASS ANALOG A 2 DIGITAL IN Easy Interface to DSPs and Microcomputers MODULATOR FILTER RFS Software Control of Filter Cutoff OUTPUT SDATA SHIFT 65 V Supply REGISTER SCLK LOW PASS ANALOG Low Power Operation: 50 mW A 3 IN DIGITAL MODULATOR FILTER DRDY APPLICATIONS Biomedical Data Acquisition LOW PASS ANALOG CONTROL A 4 DIGITAL ECG Machines IN MODULATOR REGISTER FILTER TFS EEG Machines Process Control High Accuracy Instrumentation V D 1 AGND DGND D 1 D 2 REF OUT OUT IN Seismic Systems GENERAL DESCRIPTION There are 22 bits of data corresponding to the analog input. The AD7716 is a signal processing block for data acquisition Two bits contain the channel address and 3 bits are the device systems. It is capable of processing four channels with band- address. Thus, each channel in a 32-channel system would have widths of up to 584 Hz. Resolution is 22 bits and the usable a discrete 5-bit address. The device also has a CASCOUT pin dynamic range varies from 111 dB with an input bandwidth of and a CASCIN pin that allow simple networking of multiple 36.5 Hz to 99 dB with an input bandwidth of 584 Hz. devices. The device consists of four separate A/D converter channels that The on-chip control register is programmed using the SCLK, are implemented using sigma-delta technology. Sigma-delta SDATA and TFS pins. Three bits of the Control Register set ADCs include on-chip digital filtering and, thus, the system the digital filter cutoff frequency for the device. Selectable fre- filtering requirements are eased. quencies are 584 Hz, 292 Hz, 146 Hz, 73 Hz and 36.5 Hz. A further 2 bits appear as outputs D 1 and D 2 and can be OUT OUT Three address pins program the device address. This allows a used for controlling calibration at the front end. The device is data acquisition system with up to 32 channels to be set up in a available in a 44-pin PQFP (Plastic Quad Flatpack) and 44-pin simple fashion. The output word from the device contains 32 PLCC. bits of data. One bit is determined by the state of the D 1 in- IN put and may be used, for example, in an ECG system with an external pacemaker detect circuit to indicate that the output word is invalid because of the presence of a pacemaker pulse. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 otherwise under any patent or patent rights of Analog Devices.1, 2 (f = 8 MHz MODE Pin Is High (Slave Mode Operation) AV = DV = +5 V AD7716SPECIFICATIONS CLKIN DD DD 6 5% AV = 5 V 6 5% AGND = DGND = 0 V V = 2.5 V Filter Cutoff = 146 Hz Noise Measurement Bandwidth = 146 Hz A Source SS REF IN 2 Resistance = 750 V with 1 nF to AGND at each A . T = T to T , unless otherwise noted.) IN A MIN MAX Parameter B Version Units Test Conditions/Comments STATIC PERFORMANCE Resolution 22 Bits 3 Integral Linearity Error 0.003 % FSR typ Guaranteed No Missed Codes to 21 Bits 0.006 % FSR max Gain Error 1 % FSR max Gain Match Between Channels 0.5 % FSR max Gain TC 30 V/C typ Offset Error 0.2 % FSR max Offset Match Between Channels 0.1 % FSR max Offset TC 4 V/C typ Noise 11 V rms max See Table I for Typical Noise Performance vs. Programmed Cutoff Frequency DYNAMIC PERFORMANCE Sampling Rate f /14 570 kHz for f = 8 MHz CLKIN CLKIN N Output Update Rate f /(14 3 256 3 2 ) N Is Decimal Equivalent of FC2, FC1, FC0 in Control Register CLKIN N Filter Cutoff Frequency f /(3.81 3 14 3 256 3 2 ) CLKIN N Settling Time (3 3 14 3 256 3 2 /f ) CLKIN 4 Usable Dynamic Range See Table I Total Harmonic Distortion 90 dB typ Input Frequency = 35 Hz 100 dB typ A = 10 mV p-p IN 3 N Absolute Group Delay (3 3 14 3 256 3 2 )/2f CLKIN 3 Differential Group Delay 10 ns typ Channel-to-Channel Isolation 85 dB typ Feedthrough from Any One Channel to the Other Three, with 35 Hz Full-Scale Sine Wave Applied to that Channel ANALOG INPUT Input Range 2.5 Volts Input Capacitance 10 pF typ Input Bias Current 1 nA typ LOGIC INPUTS V , Input High Voltage 2.4 V min INH V , Input Low Voltage 0.8 V max INL I , Input Current IN SDATA, RFS +10/-130 A max Internal 50 k Pull-Up Resistors TFS +10/-650 A max Internal 10 k Pull-Up Resistor All Other Inputs 10 A max 3 C , Input Capacitance 10 pF max IN LOGIC OUTPUTS V , Output High Voltage 2.4 V min I 40 A OH OUT V , Output Low Voltage 0.4 V max I 1.6 mA OL OUT POWER SUPPLIES Reference Input 2.4/2.6 V min/V max 4.75/5.25 V min/V max AVDD DV 4.75/5.25 V min/V max DD AV 4.75/5.25 V min/V max SS I 7.5 mA max 4.8 mA typ DD I 2.5 mA max 1.8 mA typ SS Power Consumption 50 mW max 35 mW typ 5 Power Supply Rejection 70 dB typ NOTES 1 Operating temperature ranges as follows : B Version 40C to +85C. 2 The A pins present a very high impedance dynamic load which varies with clock frequency. IN 3 Guaranteed by design and characterization. Digital filter has linear phase. 4 Usable dynamic range is guaranteed by measuring noise and relating this to the full-scale input range. 5 100 mV p-p, 120 Hz sine wave applied to each supply. Specifications subject to change without notice. 2 REV. A