a Dual CMOS - Modulators AD7724 FEATURES FUNCTIONAL BLOCK DIAGRAM 13 MHz Master Clock Frequency 0 V to +2.5 V or 1.25 V Input Range REF1 REF2A REF2B Single Bit Output Stream 2.5V 90 dB Dynamic Range REFERENCE Power Supplies AD7724 AVDD, DVDD: 5 V 5% DVDD1: 3 V 5% AVIN(+) - ADATA MODULATOR A Logic Outputs 3 V/5 V Compatible AVIN() On-Chip 2.5 V Voltage Reference SCLK 48-Lead LQFP BVIN(+) - BDATA MODULATOR B BVIN() XTAL OFF XTAL1 CLOCK CIRCUITRY MZERO XTAL2/MCLK GC CONTROL BIP DVAL LOGIC STBY RESET DVDD DVDD1 DGND AVDD AGND GENERAL DESCRIPTION This device consists of two seventh order sigma-delta modula- tors. Each modulator converts its analog input signal into a high speed 1-bit data stream. The part operates from a 5 V power supply and accepts a differential input range of 0 V to +2.5 V or 1.25 V centered about a common-mode bias. The analog inputs are continuously sampled by the analog modulators, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones. The original information can be digitally reconstructed with an appropriate digital filter. The part provides an accurate on-chip 2.5 V reference for each modulator. A reference input/output function is provided to allow either the internal reference or an external system refer- ence to be used as the reference source for the modulator. The device is offered in a 48-lead LQFP package and designed to operate from 40C to +85C. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 Analog Devices, Inc., 20021 (AVDD = 5 V 5% DVDD = 5 V 5%, DVDD1 = 3 V 5% AGND = DGND = 0 V, AD7724SPECIFICATIONS f = 13 MHz ac-coupled sine wave, REF2A = REF2B = 2.5 V T = T to T , unless otherwise noted.) MCLK A MIN MAX Parameter A Version Unit Test Conditions/Comments STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1 Integral Nonlinearity 0.003 % FSR typ Offset Error 0.24 % FSR typ 2 Gain Error 0.6 % FSR typ Offset Error Drift 37.69 V/C typ Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND Unipolar Mode 37.69 V/C typ Bipolar Mode 18.85 V/C typ ANALOG INPUTS Signal Input Span (VIN(+) VIN()) Bipolar Mode V /2 V max BIP = V REF2 IH Unipolar Mode 0 to V V max BIP = V REF2 IL Maximum Input Voltage AVDD V Minimum Input Voltage 0 V Input Sampling Capacitance 2 pF typ Input Sampling Rate 2 f MHz MCLK 9 Differential Input Impedance 10 /(8 f )k typ MCLK REFERENCE INPUTS REF1 Output Voltage 2.32 to 2.68 V min/max REF1 Output Voltage Drift 60 ppm/C typ REF1 Output Impedance 4 k typ Reference Buffer Offset Voltage 12 mV max Offset Between REF1 and REF2 Using Internal Reference REF2 Output Voltage 2.32 to 2.68 V min/max REF2 Output Voltage Drift 60 ppm/C typ Using External Reference REF1 = AGND 9 /(16 f )k typ REF2 Input Impedance 10 MCLK External Reference Voltage Range 2.32 to 2.68 V min/max Applied to REF1 or REF2 3 DYNAMIC SPECIFICATIONS When Tested with Ideal FIR Filter as in Figure 1 Bipolar Mode BIP = V , V = 2.5 V, VIN(+) = VIN() = 1.25 V p-p IH CM or VIN() = 1.25 V, VIN(+) = 0 V to 2.5 V Signal-to-(Noise + Distortion) 90 dB typ Input BW = 0 kHz94.25 kHz 86 dB min Total Harmonic Distortion 90 dB max Input BW = 0 kHz94.25 kHz Spurious Free Dynamic Range 90 dB max Input BW = 0 kHz94.25 kHz Unipolar Mode BIP = V , VIN() = 0 V, VIN(+) = 0 V to 2.5 V IL Signal-to-(Noise + Distortion) 88 dB typ Input BW = 0 kHz94.25 kHz Total Harmonic Distortion 90 dB typ Input BW = 0 kHz101.556 kHz Spurious Free Dynamic Range 90 dB typ Input BW = 0 kHz101.556 kHz Intermodulation Distortion 93 dB typ AC CMRR 96 dB typ VIN(+) = VIN() = 2.5 V p-p, V = 1.25 V to CM 3.75 V, 20 kHz CLOCK 4 Square Wave MCLK Duty Ratio 45 to 55 % max For Specified Operation V , MCLK High Voltage 4 V min MCLK Uses CMOS Logic MCLKH V , MCLK Low Voltage 0.4 V max MCLKL Sine Wave XTAL1 Voltage Swing 0.4 V p-p min XTAL OFF Tied Low 4 V p-p max LOGIC INPUTS V , Input High Voltage 2.4 V min IH V , Input Low Voltage 0.8 V max IL I , Input Current 10 A max INH C , Input Capacitance 10 pF max IN 2 REV. B