Dual Sigma-Delta ADC a with Auxiliary DAC AD7729 FEATURES GENERAL DESCRIPTION +3 V Supply Voltage This monolithic 3 V CMOS device is a low power, two-channel, Baseband Serial Port (BSPORT) input port with signal conditioning. The receive path is com- Differential IRx and QRx posed of two high performance sigma-delta ADCs with digital ADC Channels filtering. A common bandgap reference feeds the ADCs. Two 15-Bit Sigma-Delta A/D Converters A control DAC is included for such functions as AFC. The auxil- FIR Digital Filters iary functions can be accessed via the auxiliary port (ASPORT). 64 dB SNR Output Word Rate 270.83 kHz This device is available in a 28-lead TSSOP package or a Twos Complement Coding 28-lead SOIC package. On-Chip Offset Calibration Power-Down Mode Auxiliary D/A Converter Auxiliary Serial Port (ASPORT) On-Chip Voltage Reference Low Power 28-Lead TSSOP/28-Lead SOIC APPLICATIONS GSM Basestations Pagers FUNCTIONAL BLOCK DIAGRAM DVDD2 DVDD1 DGND AGND AVDD1 AVDD2 ASDI ASDIFS 10-BIT AUXDAC AUXDAC ASCLK AUXILIARY SERIAL ASDO INTERFACE ASDOFS ASE DECIMATION BSDI SD IRxP OFFSET FIR DIGITAL MODULATOR ADJUST IRxN BSDIFS FILTER BSCLK BASEBAND SERIAL DECIMATION QRxP OFFSET SD BSDO INTERFACE FIR DIGITAL MODULATOR ADJUST QRxN FILTER BSDOFS BSE DIVIDE BY 2 MCLK MUX RxON REFERENCE REFCAP RESETB REFOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: 1 (AVDD1 = AVDD2 = +3 V 6 10% DVDD1 = DVDD2 = +3 V 6 10% DGND = AGND = AD7729SPECIFICATIONS 0 V, f = 13 MHz RxPOWER1 = 0 RxPOWER0 = 1 MCLKDIV = 0 T = T to T unless otherwise noted) CLK A MIN MAX Parameter AD7729A Units Test Conditions/Comments REFERENCE REFCAP Absolute Voltage, V 1.3 5% V min/max REFCAP REFCAP TC 50 ppm/ C typ 0.1 m F Capacitor Required from REFCAP to AGND REFOUT Absolute Voltage, V 1.3 10% V min/max REFOUT REFOUT TC 50 ppm/ C typ 0.1 m F Capacitor Required from REFOUT to AGND ADC CHANNEL SPECIFICATIONS RxON = 1 Resolution 15 Bits ADC Signal Range 2 V V p-p REFCAP V V /2 to (AVDD V /2) Volts Differential BIAS REFCAP REFCAP V to (AVDD V ) Volts Single-Ended REFCAP REFCAP Differential Signal Range V V /2 V min/max For Both Positive and Negative Analog Inputs BIAS REFCAP Single-Ended Signal Range V V V min/max For Positive Analog Inputs Negative Analog Inputs = V BIAS REFCAP BIAS Input Sample Rate 13 MSPS Output Word Rate 270.83 kHz DC Accuracy Precalibration Offset Error 45 mV typ Post Calibration Offset Error 10 mV max Post Calibration Offset Error TC 50 m V/ C typ TC = Temperature Coefficient Input Resistance (DC) 1.23 MW typ Input Capacitance 10 pF typ Dynamic Specifications Input Frequency = 67.7 kHz Dynamic Range 67 dB typ Signal to (Noise + Distortion) 64 dB min Gain Error 1 dB max Input Frequency = 67.7 kHz, wrt 1.3 V 0.5 dB max Input Frequency = 67.7 kHz, wrt V REFCAP Gain Match Between Channels 0.2 dB max Filter Settling Time 47 m s typ Frequency Response Does Not Include Input Antialias RC Circuit 0 kHz70 kHz 0.05 dB max/min 85 kHz 1 dB max 96 kHz 3.0 dB max 135 kHz 55 dB max >170 kHz 55 dB max Absolute Group Delay 23 m s typ Group Delay Between Channels (0 kHz96 kHz) 5 ns typ Coding Twos Complement 2 AUXILIARY CONVERTER Resolution 10 Bits Output Range Code 000 2/32 V V REFCAP Offset Error 35 mV max Code 3FF 2 V V REFCAP Gain Error 60 mV min +100 mV max DC Accuracy Maximum Output for Specified Accuracy = AVDD 0.2 V or 2.6 V, Whichever Is Lower Integral Nonlinearity 4 LSB max Differential Nonlinearity 2 LSB max Guaranteed Monotonic to 9 Bits Update Rate 540 kHz max Load Resistance 10 kW min See Figure 1 Load Capacitance 50 pF max See Figure 1 I 50 m A typ SINK Full-Scale Settling Time 4 m s typ LSB Settling Time 2 m s typ Coding Binary 2 REV. 0