2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer AD7760 FEATURES FUNCTIONAL BLOCK DIAGRAM V V + 120 dB dynamic range at 78 kHz output data rate IN IN 100 dB dynamic range at 2.5 MHz output data rate 112 dB SNR at 78 kHz output data rate MULTIBIT AV 1 DD DIFF - MODULATOR AV 2 DD 100 dB SNR at 2.5 MHz output data rate AV 3 DD 2.5 MHz maximum fully filtered output word rate V REF+ AV 4 BUF RECONSTRUCTION DD Programmable oversampling rate (8 to 256) DECAPA/B Fully differential modulator input R BIAS On-chip differential amplifier for signal buffering AD7760 PROGRAMMABLE AGND DECIMATION Low-pass finite impulse response (FIR) filter with default or V DRIVE MCLK user-programmable coefficients DV CONTROL LOGIC DD I/O Modulator output mode SYNC DGND OFFSET AND GAIN REGISTERS FIR FILTER Overrange alert bit RESET ENGINE Digital offset and gain correction registers Filter bypass modes CS RD/WR DRDY DB0 TO DB15 Low power and power-down modes Figure 1. Synchronization of multiple devices via SYNC pin APPLICATIONS Data acquisition systems Vibration analysis Instrumentation GENERAL DESCRIPTION The AD7760 is a high performance, 24-bit - analog-to-digital coefficients. The sample rate, filter corner frequencies, and output converter (ADC). It combines wide input bandwidth and high word rate are set by a combination of the external clock frequency speed with the benefits of - conversion to achieve a perfor- and the configuration registers of the AD7760. mance of 100 dB SNR at 2.5 MSPS, making it ideal for high The reference voltage supplied to the AD7760 determines the speed data acquisition. Wide dynamic range combined with analog input range. With a 4 V reference, the analog input range significantly reduced antialiasing requirements simplify the is 3.2 V differential biased around a common mode of 2 V. design process. An integrated buffer to drive the reference, a This common-mode biasing can be achieved using the on-chip differential amplifier for signal buffering and level shifting, an differential amplifier, further reducing the external signal overrange flag, internal gain and offset registers, and a low-pass conditioning requirements. digital FIR filter make the AD7760 a compact, highly integrated data acquisition device requiring minimal peripheral component The AD7760 is available in an exposed paddle, 64-lead TQFP selection. In addition, the device offers programmable decimation and is specified over the industrial temperature range from rates, and the digital FIR filter can be adjusted if the default 40C to +85C. characteristics are not appropriate for the application. The Table 1. Related Devices AD7760 is ideal for applications demanding high SNR Part No. Description without a complex front-end signal processing design. AD7762 24-bit, 625 kSPS, 109 dB, - parallel interface The differential input is sampled at up to 40 MSPS by an analog AD7763 24-bit, 625 kSPS, 109 dB, - serial interface modulator. The modulator output is processed by a series of low- pass filters, with the final filter having default or user-programmable Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04975-001AD7760 TABLE OF CONTENTS Features .............................................................................................. 1 Writing to the AD7760 .............................................................. 23 Applications....................................................................................... 1 Clocking the AD7760 .................................................................... 24 Functional Block Diagram .............................................................. 1 Buffering the MCLK signal....................................................... 24 General Description ......................................................................... 1 MCLK Jitter Requirements ....................................................... 24 Revision History ............................................................................... 3 Driving the AD7760....................................................................... 26 Specifications..................................................................................... 4 Using the AD7760 ...................................................................... 27 Timing Specifications .................................................................. 6 Decoupling and Layout Recommendations................................ 28 Timing Diagrams.......................................................................... 7 Supply Decoupling ..................................................................... 29 Absolute Maximum Ratings............................................................ 8 Additional Decoupling .............................................................. 29 ESD Caution.................................................................................. 8 Reference Voltage Filtering ....................................................... 29 Pin Configuration and Function Descriptions............................. 9 Differential Amplifier Components ........................................ 29 Terminology .................................................................................... 11 Bias Resistor Selection ............................................................... 29 Typical Performance Characteristics ........................................... 12 Layout Considerations............................................................... 29 Theory of Operation ...................................................................... 18 Exposed Paddle........................................................................... 29 Modulator Data Output Mode...................................................... 19 Programmable FIR Filter............................................................... 30 Modulator Inputs........................................................................ 19 Downloading a User-Defined Filter ............................................ 31 Modulator Data Output Scaling ............................................... 19 Example Filter Download ......................................................... 31 Modulator Data Output Mode Interface ..................................... 20 AD7760 Registers ........................................................................... 33 Clock Divide-by-1 Mode (CDIV = 1) ..................................... 20 Control Register 1Address 0x0001 ...................................... 33 Control Register 2Address 0x0002 ...................................... 33 CDIV Clock Divide-by-2 Mode ( = 0) ..................................... 20 Status Register (Read Only) ...................................................... 34 Using the AD7760 in Modulator Output Mode..................... 21 Offset RegisterAddress 0x0003............................................. 34 AD7760 Interface............................................................................ 22 Gain RegisterAddress 0x0004............................................... 34 Reading Data............................................................................... 22 Overrange RegisterAddress 0x0005..................................... 34 Reading Status and Other Registers......................................... 22 Outline Dimensions ....................................................................... 35 Sharing the Parallel Bus ............................................................. 22 Ordering Guide .......................................................................... 35 Synchronization.......................................................................... 22 Rev. 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