24-Bit, 8.5 mW, 109 dB,
128 kSPS/64 kSPS/32 kSPS ADCs
AD7766
FEATURES GENERAL DESCRIPTION
Oversampled successive approximation (SAR) architecture The AD7766/AD7766-1/AD7766-2 are high performance,
High performance ac and dc accuracy, low power
24-bit, oversampled SAR analog-to-digital converters (ADCs).
115.5 dB dynamic range, 32 kSPS (AD7766-2)
The AD7766/AD7766-1/AD7766-2 combine the benefits of a
112.5 dB dynamic range, 64 kSPS (AD7766-1)
large dynamic range and input bandwidth, consuming 15 mW,
109.5 dB dynamic range, 128 kSPS (AD7766)
10.5 mW, and 8.5 mW power, respectively, and are contained in
112 dB THD
a 16-lead TSSOP package.
Exceptionally low power
Ideal for ultralow power data acquisition (such as PCI- and USB-
8.5 mW, 32 kSPS (AD7766-2)
based systems), the AD7766/AD7766-1/AD7766-2 provide 24-bit
10.5 mW, 64 kSPS (AD7766-1)
resolution. The combination of exceptional SNR, wide dynamic
15 mW, 128 kSPS (AD7766)
range, and outstanding dc accuracy make the AD7766/AD7766-1/
High dc accuracy
AD7766-2 ideally suited for measuring small signal changes over a
24 bits, no missing codes (NMC)
wide dynamic range. This is particularly suitable for applications
INL: 6 ppm (typical), 15 ppm (maximum)
where small changes on the input are measured on larger ac or
Low temperature drift
dc signals. In such an application, the AD7766/AD7766-1/
Zero error drift: 15 nV/C
AD7766-2 accurately gather both ac and dc information.
Gain error drift: 0.4 ppm/C
The AD7766/AD7766-1/AD7766-2 include an on-board digital
On-chip low-pass FIR filter
filter (complete with linear phase response) that acts to elimi-
Linear phase response
nate out-of-band noise by filtering the oversampled input voltage.
Pass-band ripple: 0.005 dB
The oversampled architecture also reduces front-end antialias
Stop-band attenuation: 100 dB
requirements. Other features of the AD7766/AD7766-1/AD7766-2
2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options
SYNC PD
Flexible interfacing options include a / (synchronization/power-down) pin, allowing
Synchronization of multiple devices the synchronization of multiple AD7766/AD7766-1/AD7766-2
Daisy-chain capability devices. The addition of an SDI pin provides the option of daisy
Power-down function chaining multiple AD7766/AD7766-1/AD7766-2 devices.
Temperature range: 40C to +105C
The AD7766/AD7766-1/AD7766-2 operate from a 2.5 V supply
using a 5 V reference. The devices operate from 40C to +105C.
APPLICATIONS
Low power PCI/USB data acquisition systems RELATED DEVICES
Low power wireless acquisition systems
Table 1. 24-Bit ADCs
Vibration analysis
Part No. Description
Instrumentation
1
AD7760 2.5 MSPS, 100 dB dynamic range, on-board differential
High precision medical acquisition
amp and reference buffer, parallel, variable decimation
1
AD7762/
FUNCTIONAL BLOCK DIAGRAM 625 kSPS, 109 dB dynamic range, on-board differential
AD7763 amp and reference buffer, parallel/serial, variable
AV AGND MCLK DV V DGND
DD DD DRIVE
decimation
1
V AD7764 312 kSPS, 109 dB dynamic range, on-board differential
REF+
amp and reference buffer, variable decimation (pin)
V
IN+
1
DIGITAL
AD7765
SUCCESSIVE 156 kSPS, 112 dB dynamic range, on-board differential
FIR FILTER
APPROXIMATION
amp and reference buffer, variable decimation (pin)
ADC
SYNC/PD
1
V
AD7767
IN 128 kSPS, 109.5 dB, 15 mW, 18-bit INL, serial interface
SERIAL INTERFACE
1
REFGND AND CS AD7767-1
64 kSPS 112.5 dB, 10.5 mW, 18-bit INL, serial interface
CONTROL LOGIC
AD7766/ 1
AD7767-2 32 kSPS, 115.5 dB, 8.5 mW, 18-bit INL, serial interface
AD7766-1/
AD7766-2
1
Dynamic range at maximum output data rate.
SCLK DRDY SDO SDI
Figure 1.
Rev. C
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06449-001AD7766
TABLE OF CONTENTS
Features .............................................................................................. 1 Supply and Reference Voltages ................................................. 16
Applications ....................................................................................... 1 AD7766/AD7766-1/AD77662-2 Interface .................................. 17
Functional Block Diagram .............................................................. 1 Initial Power-Up ......................................................................... 17
General Description ......................................................................... 1 Reading Data ............................................................................... 17
Related Devices ................................................................................. 1 Power-Down, Reset, and Synchronization ............................. 17
Revision History ............................................................................... 2 Daisy Chaining ............................................................................... 18
Specif icat ions ..................................................................................... 3 Reading Data in Daisy-Chain Mode ....................................... 18
Timing Specifications .................................................................. 5 Choosing the SCLK Frequency ................................................ 18
Timing Diagrams .......................................................................... 6 Daisy-Chain Mode Configuration and Timing Diagrams ... 19
Absolute Maximum Ratings ............................................................ 8 Driving the AD7766/AD7766-1/AD7766-2 ............................... 20
ESD Caution .................................................................................. 8 Differential Signal Source ......................................................... 20
Pin Configuration and Function Descriptions ............................. 9 Single-Ended Signal Source ...................................................... 20
Typical Performance Characteristics ........................................... 10 Antialiasing ................................................................................. 21
Terminology .................................................................................... 14 Power Dissipation....................................................................... 21
Theory of Operation ...................................................................... 15 V Input Signal ....................................................................... 22
REF+
AD7766/AD7766-1/AD7766-2 Transfer Function ................ 15 Multiplexing Analog Input Channels ...................................... 22
Converter Operation .................................................................. 15 Outline Dimensions ....................................................................... 23
Analog Input Structure .............................................................. 16 Ordering Guide .......................................................................... 23
REVISION HISTORY
4/10Rev. B to Rev. C
Changes to Pin 8 Description ......................................................... 9
Changes to Table 8 .......................................................................... 20
3/09Rev. A to Rev. B
Changes to t Parameter, Table 3 .......................................... 5
SETTLING
Changes to Table 7 .......................................................................... 17
1/09Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Change to AD7766, Intermodulation Distortion (IMD)
Parameter and Integral Nonlinearity Parameter, Table 2 ....... 3
Change to Figure 21 and Figure 24 .............................................. 12
Changes to Supply and Reference Voltages Section ................... 16
Changes to Choosing the SCLK Frequency Section .................. 18
Changes to Driving the AD7766 Section .................................... 20
Changes to Single-Ended Signal Source Section ........................ 20
Changes to Figure 40 and Figure 41 ............................................. 20
Added Table 8; Renumbered Sequentially .................................. 20
Change to Figure 42 ....................................................................... 21
Changes to Antialiasing Section ................................................... 21
Changes to Table 9 .......................................................................... 21
Changes to V
REF+ Input Signal Section ......................................... 22
Changes to Figure 46 ...................................................................... 22
8/07Revision 0: Initial Version
Rev. C | Page 2 of 24