DC to 204 kHz, Dynamic Signal Analysis, Precision 24-Bit ADC with Power Scaling Data Sheet AD7768-1 Power supply FEATURES AVDD1 AVSS = 5.0 V typical ADC for single-channel low power, platform DAQ designs AVDD2 AVSS = 2.0 V to 5.0 V typical Wide bandwidth Analog supplies can run from split supply (true bipolar) Sinc filter bandwidth range: DC to 204 kHz IOVDD DGND = 1.8 V to 3.3 V typical Low ripple FIR bandwidth range: DC to 110.8 kHz Low power mode can run from single 3.0 V supply Precision ac and dc performance Pin control or SPI interface configurable 108.5 dB dynamic range typical Suite of diagnostic check mechanisms 120 dB THD Temperature, interface CRC, and memory map CRC 1.1 ppm of FSR INL, 30 V offset error, 30 ppm of FSR Package: 28-lead, 4 mm 5 mm, LFCSP gain error Temperature range: 40C to +125C Programmable ODR, filter type, and latency ODR values up to 1024 kSPS APPLICATIONS Linear phase digital filter options Platform ADC to serve a superset of measurements and Low ripple FIR filter: 0.005 dB maximum pass-band sensor types ripple, dc to 102.4 kHz Sound and vibration, acoustic, and material science Low latency sinc5 filter research and development Low latency sinc3 filter enabling 50 Hz/60 Hz rejection Control and hardware in loop verification Programmable FIR filter option Condition monitoring for predictive maintenance Programmable power consumption and bandwidth Electrical test and measurement Fast, highest speed Audio testing and current and voltage measurement 52.224 kHz bandwidth, 26.4 mW (sinc5 filter) Clinical electroencephalogram (EEG), electromyogram 110.8 kHz bandwidth, 36.8 mW (FIR filter) (EMG), and electrocardiogram (ECG) vital signs Median, half speed: 55.4 kHz bandwidth, 19.7 mW (FIR filter) monitoring Low power, low speed: 13.9 kHz bandwidth, 6.75 mW USB-, PXI-, and Ethernet-based modular DAQ (FIR filter) Channel to channel isolated modular DAQ designs FUNCTIONAL BLOCK DIAGRAM AVDD1 REF+ REF DGND AVDD2 REGCAPA REGCAPD IOVDD AD7768-1 SYNC IN 1.8V 1.8V SYNC OUT 2 REFERENCE VCM LDO LDO BUFFERS RESET DRDY WIDEBAND ADC LOW RIPPLE CS DATA FILTER DOUT/RDY SERIAL SDI AIN+ INTERFACE POWER SINC5 LOW LATENCY SCLK SCALABLE FILTER AIN - ADC SINC3 FILTER CONTROL ENABLING BLOCK 50Hz/60Hz PRECHARGE REJECTION BUFFERS AVSS MCLK/XTAL2 XTAL1 CLKSEL MODE3 TO MODE0 PIN/SPI (GPIO3 TO GPIO0) Figure 1. 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Technical Support www.analog.com 16481-001AD7768-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Electromagnetic Compatibility (EMC) Testing ..................... 64 Applications ....................................................................................... 1 AD7768-1 Subsystem Layout ................................................... 65 Functional Block Diagram .............................................................. 1 Register Summary .......................................................................... 66 Revision History ............................................................................... 3 Register Details ............................................................................... 68 General Description ......................................................................... 4 Component Type Register ......................................................... 68 Specifications ..................................................................................... 5 Unique Product ID Registers .................................................... 68 3 V Operation.............................................................................. 10 Device Grade and Revision Register ....................................... 68 Timing Specifications ................................................................ 11 User Scratchpad Register ........................................................... 68 1.8 V Timing Specifications ...................................................... 12 Device Vendor ID Registers ...................................................... 68 Absolute Maximum Ratings .......................................................... 17 Interface Format Control Register ........................................... 69 Thermal Resistance .................................................................... 17 Power and Clock Control Register........................................... 69 ESD Caution ................................................................................ 17 Analog Buffer Control Register ................................................ 70 Pin Configuration and Function Descriptions ........................... 18 VCM Control Register ............................................................... 71 Typical Performance Characteristics ........................................... 20 Conversion Source Select and Mode Control Register ......... 71 Terminology .................................................................................... 28 Digital Filter and Decimation Control Register ..................... 72 Theory of Operation ...................................................................... 29 Sinc3 Decimation Rate (MSB Register) .................................. 73 Clocking, Sampling Tree, and Power Scaling ......................... 29 Sinc3 Decimation Rate (LSB Register) .................................... 73 Noise Performance and Resolution.......................................... 30 Periodic Conversion Rate Control Register ............................ 73 Core Converter ........................................................................... 32 Synchronization Modes and Reset Triggering Register ........ 74 Clocking and Clock Selection ................................................... 35 GPIO Port Control Register ...................................................... 74 Digital Filtering ........................................................................... 35 GPIO Output Control Register ................................................ 75 Decimation Rate Control .......................................................... 40 GPIO Input Read Register ........................................................ 75 Antialiasing Filtering ................................................................. 40 Offset Calibration MSB Register .............................................. 75 Getting Started ............................................................................ 41 Offset Calibration MID Register .............................................. 75 Power Supplies ............................................................................ 43 Offset Calibration LSB Register ............................................... 76 Device Configuration Method ................................................. 43 Gain Calibration MSB Register ................................................ 76 Pin Control Mode Overview .................................................... 44 Gain Calibration MID Register ................................................ 76 SPI Control Overview ................................................................ 47 Gain Calibration LSB Register .................................................. 76 SPI Control Mode ....................................................................... 48 SPI Interface Diagnostic Control Register .............................. 77 Digital Interface .............................................................................. 51 ADC Diagnostic Feature Control Register ............................. 77 Data Conversion Modes ............................................................ 55 Digital Diagnostic Feature Control Register .......................... 77 Synchronization of Multiple AD7768-1 Devices .................... 56 Conversion Result Register ....................................................... 77 Additional Functionality of the AD7768-1 ............................. 58 Device Error Flags Master Register ......................................... 78 Applications Information .............................................................. 59 SPI Interface Error Register ...................................................... 78 Analog Input Recommendations ............................................. 59 ADC Diagnostics Output Register ........................................... 78 Antialiasing Filter Design Considerations .............................. 60 Digital Diagnostics Output Register ........................................ 79 Recommended Interface ........................................................... 61 MCLK Diagnostic Output Register ......................................... 79 Programmable Digital Filter ..................................................... 62 Coefficient Control Register ..................................................... 79 Rev. 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