8-/4-Channel, 24-Bit, Simultaneous Sampling ADCs with Power Scaling, 110.8 kHz BW Data Sheet AD7768/AD7768-4 FEATURES Linear phase digital filter Precision ac and dc performance Low latency sinc5 filter 8-/4-channel simultaneous sampling Wideband brick wall filter: 0.005 dB ripple to 102.4 kHz 256 kSPS maximum ADC ODR per channel Analog input precharge buffers 108 dB dynamic range Power supply 110.8 kHz maximum input bandwidth (3 dB BW) AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V 120 dB THD, typical IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V 2 ppm of full-scale range (FSR) integral nonlinearity 64-lead LQFP package, no exposed pad (INL), 50 V offset error, 30 ppm gain error Temperature range: 40C to +105C Optimized power dissipation vs. noise vs. input bandwidth APPLICATIONS Selectable power, speed, and input bandwidth Data acquisition systems: USB/PXI/Ethernet Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel Instrumentation and industrial control loops Median (half speed): 55.4 kHz BW, 27.5 mW per channel Audio testing and measurement Low power (lowest power): 13.8 kHz BW, 9.375 mW per Vibration and asset condition monitoring channel 3-phase power quality analysis Input BW range: dc to 110.8 kHz Sonar Programmable input bandwidth/sampling rates High precision medical electroencephalogram (EEG)/ CRC error checking on data interface electromyography (EMG)/electrocardiogram (ECG) Daisy-chaining FUNCTIONAL BLOCK DIAGRAM AVDD1A, AVDD2A, REGCAPA, AVDD1B REFx+ REFx AVDD2B REGCAPB DGND IOVDD DREGCAP BUFFERED VCM 1.8V 1.8V PRECHARGE VCM 8 REFERENCE LDO LDO VCM BUFFERS SYNC IN SYNC OUT START AIN0+ P OFFSET, - RESET CH 0 DIGITAL GAIN PHASE ADC FILTER CORRECTION AIN0 P FORMAT1* ENGINE FORMAT0 AIN1+ P OFFSET, - CH 1 GAIN PHASE ADC ADC AIN1 P CORRECTION OUTPUT DRDY SINC5 DATA AIN2+ LOW LATENCY P SERIAL DCLK OFFSET, - FILTER CH 2 INTERFACE GAIN PHASE DOUT0 ADC AIN2 P CORRECTION DOUT1 DOUT2 AIN3+ P OFFSET, - DOUT3 CH 3 GAIN PHASE ADC AIN3 P CORRECTION DOUT4* DOUT5* WIDEBAND AIN4+ P LOW RIPPLE DOUT6*, DIN OFFSET, - CH 4* FILTER GAIN PHASE ADC DOUT7* AIN4 P CORRECTION AIN5+ P OFFSET, - CH 5* GAIN PHASE ADC AIN5 ST0/CS P CORRECTION SPI ST1*/SCLK CONTROL INTERFACE AIN6+ P DEC0/SDO OFFSET, - CH 6* GAIN PHASE DEC1/SDI ADC P CORRECTION AIN6 AIN7+ P OFFSET, - PIN/SPI CH 7* GAIN PHASE ADC CORRECTION AIN7 P 16 ANALOG INPUT PRECHARGE BUFFERS (P) AD7768/AD7768-4 AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3 FILTER/GPIO4 TO *THESE CHANNELS/PINS EXIST ONLY ON THE AD7768. MODE0/GPIO0 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 14001-001AD7768/AD7768-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 AD7768 Register Map Details (SPI Control) .............................. 78 Applications ....................................................................................... 1 AD7768 Register Map................................................................ 78 Functional Block Diagram .............................................................. 1 Channel Standby Register ......................................................... 80 Revision History ............................................................................... 3 Channel Mode A Register ......................................................... 80 General Description ......................................................................... 5 Channel Mode B Register ......................................................... 81 Specif icat ions ..................................................................................... 6 Channel Mode Select Register .................................................. 81 1.8 V IOVDD Specifications ..................................................... 13 Power Mode Select Register ...................................................... 82 Timing Specifications ................................................................ 17 General Device Configuration Register .................................. 83 1.8 V IOVDD Timing Specifications ....................................... 18 Data Control: Soft Reset, Sync, and Single-Shot Control Register ........................................................................................ 83 Absolute Maximum Ratings .......................................................... 22 Interface Configuration Register .............................................. 84 Thermal Resistance .................................................................... 22 Digital Filter RAM Built In Self Test (BIST) Register............ 85 ESD Caution ................................................................................ 22 Status Register ............................................................................. 85 Pin Configurations and Function Descriptions ......................... 23 Revision Identification Register ............................................... 85 Typical Performance Characteristics ........................................... 31 GPIO Control Register .............................................................. 86 Terminology .................................................................................... 41 GPIO Write Data Register ......................................................... 86 Theory of Operation ...................................................................... 42 GPIO Read Data Register .......................................................... 87 Clocking, Sampling Tree, and Power Scaling ............................. 42 Analog Input Precharge Buffer Enable Register Channel 0 to Noise Performance and Resolution .......................................... 43 Channel 3 .................................................................................... 87 Applications Information .............................................................. 45 Analog Input Precharge Buffer Enable Register Channel 4 to Power Supplies ............................................................................ 46 Channel 7 .................................................................................... 87 Device Configuration ................................................................ 47 Positive Reference Precharge Buffer Enable Register ............ 88 Pin Control .................................................................................. 47 Negative Reference Precharge Buffer Enable Register .......... 88 SPI Control .................................................................................. 50 Offset Registers ........................................................................... 89 SPI Control Functionality ......................................................... 51 Gain Registers ............................................................................. 89 SPI Control Mode Extra Diagnostic Features ........................ 54 Sync Phase Offset Registers ...................................................... 90 Circuit Information ........................................................................ 55 ADC Diagnostic Receive Select Register ................................ 90 Core Signal Chain ....................................................................... 55 ADC Diagnostic Control Register ........................................... 91 Analog Inputs .............................................................................. 56 Modulator Delay Control Register ........................................... 91 VCM ............................................................................................. 58 Chopping Control Register ....................................................... 91 Reference Input ........................................................................... 58 AD7768-4 Register Map Details (SPI Control) .......................... 92 Clock Selection ........................................................................... 58 AD7768-4 Register Map ............................................................ 92 Digital Filtering ........................................................................... 58 Channel Standby Register ......................................................... 94 Decimation Rate Control .......................................................... 62 Channel Mode A Register ......................................................... 94 Antialiasing ................................................................................. 62 Channel Mode B Register ......................................................... 95 Calibration ................................................................................... 64 Channel Mode Select Register .................................................. 95 Data Interface .................................................................................. 66 Power Mode Select Register ...................................................... 95 Setting the Format of Data Output .......................................... 66 General Device Configuration Register .................................. 96 ADC Conversion Output: Header and Data .......................... 67 Data Control: Soft Reset, Sync, and Single-Shot Control Functionality ................................................................................... 77 Register ........................................................................................ 97 GPIO Functionality .................................................................... 77 Interface Configuration Register .............................................. 97 Rev. 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