8-Channel, 24-Bit, Simultaneous Sampling ADC Data Sheet AD7779 chain. The AD7779 accepts V from 1 V up to 3.6 V. The FEATURES REF analog inputs accept unipolar (0 V to VREF/GAIN) or true bipolar 8-channel, 24-bit simultaneous sampling analog-to-digital (VREF/GAIN/2 V) analog input signals with 3.3 V or 1.65 V converter (ADC) analog supply voltages. The analog inputs can be configured to Single-ended or true differential inputs accept true differential, pseudo differential, or single-ended signals Programmable gain amplifier (PGA) per channel (gains of 1, 2, 4, and 8) to match different sensor output configurations. Low dc input current Each channel contains an ADC modulator and a sinc3, low 1.5 nA (differential) latency digital filter. An SRC is provided to allow fine resolution 4 nA (single-ended) control over the AD7779 ODR. This control can be used in Up to 16 kSPS output data rate (ODR) per channel applications where the ODR resolution is required to maintain Programmable ODRs and bandwidth coherency with 0.01 Hz changes in the line frequency. The SRC Sample rate converter (SRC) for coherent sampling is programmable through the serial port interface (SPI). The Sampling rate resolution up to 15.2 SPS AD7779 implements two different interfaces: a data output Low latency sinc3 filter path interface and SPI control interface. The ADC data output Adjustable phase synchronization interface is dedicated to transmitting the ADC conversion results Internal 2.5 V reference from the AD7779 to the processor. The SPI interface is used to Two power modes optimizing power dissipation and write to and read from the AD7779 configuration registers and performance: high resolution mode and low power mode Low resolution successive approximation (SAR) ADC for for the control and reading of data from the SAR ADC. The SPI system and chip diagnostics interface can also be configured to output the - conversion data. Power supply The AD7779 includes a 12-bit SAR ADC. This ADC can be used Bipolar (1.65 V) or unipolar (3.3 V) supplies for AD7779 diagnostics without having to decommission one of Digital input/output (I/O) supply: 1.8 V to 3.6 V the - ADC channels dedicated to system measurement func- Performance temperature range: 40C to +105C tions. With the use of an external multiplexer, which can be Functional temperature range: 40C to +125C controlled through the three general-purpose inputs/outputs pins Performance (GPIOs), and signal conditioning, the SAR ADC can be used to Combined ac and dc performance validate the - ADC measurements in applications where 108 dB signal-to-noise ratio (SNR)/dynamic range at 16 kSPS functional safety is required. In addition, the AD7779 SAR ADC in high resolution mode includes an internal multiplexer to sense internal nodes. 109 dB total harmonic distortion (THD) 7 ppm integral nonlinearity (INL) The AD7779 contains a 2.5 V reference and reference buffer. 40 V offset error The reference has a typical temperature coefficient of 10 ppm/C. 0.1% gain error The AD7779 offers two modes of operation: high resolution mode 10 ppm/C typical temperature coefficient and low power mode. High resolution mode provides a higher APPLICATIONS dynamic range while consuming 10.75 mW per channel low Circuit breakers power mode consumes just 3.37 mW per channel at a reduced General-purpose data acquisition dynamic range specification. Electroencephalography (EEG) The specified operating temperature range is 40C to +105C, Industrial process control although the device is operational up to +125C. GENERAL DESCRIPTION Note that throughout this data sheet, certain terms are used to The AD7779 is an 8-channel, simultaneous sampling ADC. There refer to either the multifunction pins or a range of pins. The are eight full - ADCs on chip. The AD7779 provides an ultra- multifunction pins, such as DCLK0/SDO, are referred to either by low input current to allow direct sensor connection. Each input the entire pin name or by a single function of the pin, for example, channel has a programmable gain stage allowing gains of 1, 2, 4, DCLK0, when only that function is relevant. In the case of ranges and 8 to map lower amplitude sensor outputs into the full-scale of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B, ADC input range, maximizing the dynamic range of the signal AVSS2A, AVSS2B, AVSS3, and AVSS4. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20162020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. AD7779 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Monitoring Using the AD7779 SAR ADC (SPI Control Mode) ........................................................................................... 48 Applications ...................................................................................... 1 - ADC Diagnostics (SPI Control Mode) ........................... 50 General Description ......................................................................... 1 - Output Data ............................................................................. 51 Revision History ............................................................................... 4 ADC Conversion OutputHeader and Data ........................ 51 Functional Block Diagram .............................................................. 5 Sample Rate Converter (SRC) (SPI Control Mode) .............. 52 Specifications .................................................................................... 6 Data Output Interface ............................................................... 54 DOUTx Timing Characterististics ........................................... 10 Calculating the CRC Checksum .............................................. 58 SPI Timing Characterististics ................................................... 11 Register Summary .......................................................................... 60 Synchronization Pins and Reset Timing Characteristics ..... 12 Register Details ............................................................................... 65 SAR ADC Timing Characterististics ....................................... 13 Channel 0 Configuration Register ........................................... 65 GPIO SRC Update Timing Characterististics ........................ 13 Channel 1 Configuration Register ........................................... 65 Absolute Maximum Ratings ......................................................... 14 Channel 2 Configuration Register ........................................... 66 Thermal Resistance .................................................................... 14 Channel 3 Configuration Register ........................................... 66 ESD Caution................................................................................ 14 Channel 4 Configuration Register ........................................... 67 Pin Configuration and Function Descriptions .......................... 15 Channel 5 Configuration Register ........................................... 67 Typical Performance Characteristics ........................................... 18 Channel 6 Configuration Register ........................................... 68 Terminology .................................................................................... 31 Channel 7 Configuration Register ........................................... 68 RMS Noise and Resolution ........................................................... 33 Disable Clocks to ADC Channel Register .............................. 69 High Resolution Mode .............................................................. 33 Channel 0 Sync Offset Register ................................................ 69 Low Power Mode ....................................................................... 33 Channel 1 Sync Offset Register ................................................ 69 Theory of Operation ...................................................................... 34 Channel 2 Sync Offset Register ................................................ 70 Analog Inputs ............................................................................. 34 Channel 3 Sync Offset Register ................................................ 70 Transfer Function ...................................................................... 35 Channel 4 Sync Offset Register ................................................ 70 Core Signal Chain ...................................................................... 36 Channel 5 Sync Offset Register ................................................ 70 Capacitive PGA .......................................................................... 36 Channel 6 Sync Offset Register ................................................ 71 Internal Reference and Reference Buffers .............................. 36 Channel 7 Sync Offset Register ................................................ 71 Integrated LDOs ......................................................................... 37 General User Configuration 1 Register ................................... 71 Clocking and Sampling ............................................................. 37 General User Configuration 2 Register ................................... 72 Digital Reset and Synchronization Pins .................................. 37 General User Configuration 3 Register ................................... 73 Digital Filtering ........................................................................... 38 Data Output Format Register ................................................... 73 Shutdown Mode ......................................................................... 38 Main ADC Meter and Reference Mux Control Register ...... 74 Controlling the AD7779 ............................................................ 39 Global Diagnostics Mux Register ............................................ 75 Pin Control Mode ...................................................................... 39 GPIO Configuration Register ................................................... 76 SPI Control .................................................................................. 41 GPIO Data Register ................................................................... 76 Digital SPI Interface ................................................................... 44 Buffer Configuration 1 Register ............................................... 76 Diagnostics and Monitoring ......................................................... 47 Buffer Configuration 2 Register ............................................... 77 Self Diagnostics Error ................................................................ 47 Channel 0 Offset Upper Byte Register .................................... 77 Rev. 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