2:1 HDMI/DVI Switch with Equalization and DDC/CEC Buffers AD8192 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET 2 inputs, 1 output HDMI/DVI links SERIAL INTERFACE HDMI 1.3a receive and transmit compliant AD8192 AVCC I2C SDA DVCC CONFIG CONTROL 7 kV HBM ESD on HDMI input pins I2C SCL AMUXVCC INTERFACE LOGIC I2C ADDR AVEE DVEE 4 TMDS channels per link VREF AB VREF COM Supports 250 Mbps to 2.25 Gbps data rates and beyond VTTI Supports 25 MHz to 225 MHz pixel clocks and beyond VTTO 4 Fully buffered unidirectional inputs/outputs IP A 3:0 IN A 3:0 4 Switchable 50 on-chip input terminations with 4 + OP 3:0 SWITCH ON 3:0 CORE EQ PE 4 programmable or automatic control on channel switch 4 IP B 3:0 Equalized inputs and pre-emphasized outputs IN B 3:0 4 Low added jitter HIGH SPEED BUFFERED VTTI Output disable feature for reduced power dissipation 2 Switched output termination for building of larger arrays DDC A 1:0 SWITCH 2 DDC COM 1:0 Bidirectional and cascadable DDC buffers (SDA/SCL) CORE 2 DDC B 1:0 DDC bus logic level translation (3.3 V, 5 V) Bidirectional and cascadable CEC buffer with integrated CEC I/O CEC O/I pull-up resistors (27 k) BUFFERED LOW SPEED HPD A Hot plug detect pulse low on channel switch HPD B BIDIRECTIONAL 2 Standards compatible: DVI, HDMI 1.3a, HDCP, I C DVEE 2 Serial (I C slave) control interface Figure 1. 56-lead, 8 mm 8 mm LFCSP, RoHS-compliant package TYPICAL APPLICATION HDTV SET APPLICATIONS HDMI Front panel buffer for advanced television (HDTV) sets RECEIVER SET-TOP BOX DVD PLAYER Standalone HDMI switcher Multiple input displays AD8192 Projectors A/V receivers Figure 2. Typical Application for HDTV Sets Set-top boxes GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD8192 is a complete HDMI/DVI link switch featuring 1. Fully HDMI 1.3a transmit and receive compliant. equalized TMDS inputs and pre-emphasized TMDS outputs 2. Supports data rates up to 2.25 Gbps, enabling greater than ideal for systems with long cable runs. The TMDS outputs can 1080p HDMI formats with deep color (12-bit) and UXGA be set to a high impedance state to reduce the power dissipation (1600 1200) DVI resolutions. and/or allow the construction of larger arrays using the wire- 3. Input cable equalizer enables use of long cables more than OR technique. The AD8192 includes bidirectional buffering for 20 m (24 AWG) at data rates up to 2.25 Gbps. the DDC bus and CEC line, with integrated pull-up resistors for 4. Auxiliary switch isolates and buffers the DDC bus and the the CEC line. The AD8192 is available in a space-saving, 56-lead CEC line, improving total system capacitance limit. LFCSP surface-mount, lead-free plastic package specified to 5. Hot plug detect (HPD) signal is pulsed low on link switch. operate over the 40C to +85C temperature range. 6. Manually or automatically switched input terminations. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2008 Analog Devices, Inc. All rights reserved. 07050-002 07050001 + +AD8192 TABLE OF CONTENTS Features .............................................................................................. 1 Write Procedure .......................................................................... 15 Applications ....................................................................................... 1 Read Procedure ........................................................................... 16 Functional Block Diagram .............................................................. 1 Configuration Registers ................................................................. 17 Typical Application ........................................................................... 1 High Speed Device Modes Register ......................................... 18 General Description ......................................................................... 1 Auxiliary Device Modes Register ............................................. 18 Product Highlights ........................................................................... 1 Receiver Settings Register ......................................................... 18 Revision History ............................................................................... 2 Input Termination Control Register ........................................ 18 Specif icat ions ..................................................................................... 3 Receive Equalizer Register ........................................................ 18 Absolute Maximum Ratings ............................................................ 5 Transmitter Settings Register .................................................... 19 Thermal Resistance ...................................................................... 5 Source Sign Control Register .................................................... 19 ESD Caution .................................................................................. 5 Source A Input/Output Mapping Register .............................. 19 Pin Configuration and Function Descriptions ............................. 6 Source B Input/Output Mapping Register .............................. 19 Typical Performance Characteristics ............................................. 8 Applications Information .............................................................. 20 Theory of Operation ...................................................................... 12 Pinout ........................................................................................... 20 Input Channels ............................................................................ 12 Cable Lengths and Equalization ............................................... 21 Output Channels ........................................................................ 12 TMDS Output Rise/Fall Times ................................................. 21 Switching Mode .......................................................................... 13 Front Panel Buffer for Advanced TV ....................................... 21 Pre-Emphasis .............................................................................. 13 HDMI Switcher .......................................................................... 21 Auxiliary Multiplexer ................................................................. 14 Cascading Multiple Devices ...................................................... 21 DDC Logic Levels ....................................................................... 14 PCB Layout Guidelines .............................................................. 22 Input/Output Mapping Control ............................................... 14 Outline Dimensions ....................................................................... 25 Serial Control Interface .................................................................. 15 Ordering Guide .......................................................................... 25 Reset ............................................................................................. 15 REVISION HISTORY 5/08Revision 0: Initial Version Rev. 0 Page 2 of 28