AD8195ACPZ Analog Devices

HDMI/DVI Buffer with Equalization Data Sheet AD8195 FEATURES FUNCTIONAL BLOCK DIAGRAM 1 input, 1 output HDMI/DVI link Enables HDMI 1.3a-compliant front panel input 4 TMDS channels per link PARALLEL AVCC Supports 250 Mbps to 2.25 Gbps data rates AD8195 AMUXVCC VTTI Supports 25 MHz to 225 MHz pixel clocks AVEE CONTROL LOGIC Equalized inputs for operation with long HDMI cables VTTO (20 m at 2.25 Gbps) + 4 4 + IP 3:0 OP 3:0 Preemphasized outputs BUFFER 4 4 IN 3:0 EQ PE ON 3:0 Fully buffered unidirectional inputs/outputs HIGH SPEED BUFFERED 50 on-chip terminations VREF IN VREF OUT Low added jitter SCL IN SCL OUT Transmitter disable feature 2 2 SDA IN SDA OUT Reduces power dissipation Disables input termination CEC IN CEC OUT 3 auxiliary buffered channels per link Bidirectional buffered DDC lines (SDA and SCL) LOW SPEED BUFFERED Bidirectional buffered CEC line with integrated pull-up BIDIRECTIONAL resistors (27 k) Independently powered from 5 V of HDMI input Figure 1. connector Logic level translation (3.3 V, 5 V) Input/output capacitance isolation TYPICAL APPLICATION Standards compatible: HDMI, DVI, HDCP, DDC, CEC HDTV SET MEDIA CENTER 40-lead LFCSP VQ package (6 mm 6 mm) GAME HDMI CONSOLE RECEIVER APPLICATIONS SET-TOP BOX Front panel buffer for advanced television (HDTV) sets 4:1 HDMI AD8195 SWITCH DVD PLAYER GENERAL DESCRIPTION BACK PANEL FRONT PANEL CONNECTORS CONNECTOR The AD8195 is an HDMI/DVI buffer featuring equalized TMDS Figure 2. Typical AD8195 Application for HDTV Sets inputs and preemphasized TMDS outputs, ideal for systems with long cable runs. The AD8195 includes bidirectional buffering for the DDC bus and bidirectional buffering with integrated PRODUCT HIGHLIGHTS pull-up resistors for the CEC bus. The DDC and CEC buffers 1. Enables a fully HDMI 1.3a-compliant front panel input. are powered independently of the TMDS buffers so that DDC/ 2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep CEC functionality can be maintained when the system is powered color (12-bit color) HDMI formats and greater than UXGA off. The AD8195 meets all the requirements for sink tests as (1600 1200) DVI resolutions. defined in Section 8 of the HDMI Compliance Test 1.3c. 3. Input cable equalizer enables use of long cables more than The AD8195 is specified to operate over the 40C to +85C 20 meters (24 AWG) at data rates of up to 2.25 Gbps. temperature range. 4. Auxiliary buffer isolates and buffers the DDC bus and CEC line for a single chip, fully HDMI 1.3a-compliant solution. 5. Auxiliary buffer is powered independently from the TMDS link so that DDC/CEC functionality can be maintained when the system is powered off. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PE EN TX EN COMP 07049-002 07049-001AD8195 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 Input Channels ........................................................................... 13 Typical Application ........................................................................... 1 Output Channels ........................................................................ 13 Product Highlights ........................................................................... 1 Preemphasis ................................................................................ 14 Revision History ............................................................................... 2 Auxiliary Lines ............................................................................ 14 Specifications ..................................................................................... 3 Applications Information .............................................................. 15 TMDS Performance Specifications ............................................ 3 Front Panel Buffer for Advanced TV ....................................... 15 Auxiliary Channel Performance Specifications........................ 4 Cable Lengths and Equalization ............................................... 16 Power Supply and Control Logic Specifications ...................... 4 TMDS Output Rise/Fall Times ................................................. 16 Absolute Maximum Ratings ............................................................ 5 PCB Layout Guidelines .............................................................. 16 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 19 Maximum Power Dissipation ..................................................... 5 Ordering Guide .......................................................................... 19 ESD Caution .................................................................................. 5 REVISION HISTORY 8/12Rev. A to Rev. B 8/11Rev. 0 to Rev. A Changed Data Rate = 3 Gbps to Changed Data Rate = 2.25 Gbps to Data Rate = 2.25 Gbps .................................................. Throughout Data Rate = 2.25 Gbps .................................................. Throughout Changes to Features Section, General Description Section, and Changes to Features Section, General Description Section, and Product Highlights Section ............................................................. 1 Product Highlights Section .............................................................. 1 Changes to Table 1 ............................................................................ 3 Changes to Table 1 ............................................................................. 3 Changes to specifications statements in Typical Performance Changes to Table 3 ............................................................................. 4 Characteristics Section ..................................................................... 8 Changes to Figure 5 Caption and Figure 7 Caption ..................... 8 Changes to Figure 19 ...................................................................... 11 Added Figure 6 and Figure 8 Renumbered Sequentially ............ 8 Changes to Theory of Operation Section and to Moved Figure 9 and Figure 11 ......................................................... 9 Input Channels Section .................................................................. 13 Changes to Figure 9 Caption and Figure 11 Caption ................... 9 Changes to Output Channels Section .......................................... 13 Added Figure 10 and Figure 12 ....................................................... 9 Changes to Preemphasis Section .................................................. 14 Moved Figure 14 and Figure 16 .................................................... 10 Changes to Cable Lengths and Equalization Section and Changes to Figure 14 Caption and Figure 16 Caption .............. 10 PCB Layout Guidelines Section .................................................... 16 Added Figure 15 and Figure 17 .................................................... 10 Added Unused DDC/CEC Buffers Section ................................. 18 Changes to Figure 18, Figure 19, and Figure 21 ......................... 11 Changes to Input Channels Section ............................................. 13 Changes to Output Channels Section .......................................... 13 Changes to Preemphasis Section .................................................. 14 Changes to Cable Lengths and Equalization Section, TMDS Output Rise/Fall Times Section, and PCB Layout Guidelines Section .............................................................................................. 16 Changes to Auxiliary Control Signals Section ........................... 18 8/08Revision 0: Initial Version Rev. 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