Radar Receive Path AFE: 6-Channel LNA/PGA/AAF with ADC Data Sheet AD8283 FEATURES FUNCTIONAL BLOCK DIAGRAM 6 channels of LNA, PGA, AAF 1 channel of direct-to-ADC Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) INA+ REFERENCE LNA PGA AAF SPI-programmable gain = 16 dB to 34 dB in 6 dB steps INA Antialiasing filter (AAF) INB+ LNA PGA AAF INB Programmable third-order low-pass elliptic filter (LPF) from DSYNC 1 MHz to 12 MHz INC+ LNA PGA AAF INC Analog-to-digital converter (ADC) 12-BIT MUX D 0:11 DRV ADC 12 bits of accuracy up to 72 MSPS IND+ LNA PGA AAF IND SNR = 67 dB SFDR = 68 dB INE+ LNA PGA AAF INE Low power, 170 mW per channel at 12 bits/72 MSPS Low noise, 3.5 nV/Hz maximum of input referred INF+ LNA PGA AAF INF voltage noise INADC+ Power-down mode INADC 72-lead, 10 mm 10 mm, LFCSP package SPI Specified from 40C to +105C Qualified for automotive applications AD8283 APPLICATIONS Automotive radar Figure 1. Adaptive cruise control Collision avoidance Blind spot detection Self-parking Electronic bumper GENERAL DESCRIPTION The AD8283 is designed for low cost, low power, compact size, Fabricated in an advanced CMOS process, the AD8283 is flexibility, and ease of use. It contains six channels of a low noise available in a 10 mm 10 mm, RoHS-compliant, 72-lead preamplifier (LNA) with a programmable gain amplifier (PGA) LFCSP. It is specified over the automotive temperature range and an antialiasing filter (AAF) plus one direct-to-ADC of 40C to +105C. channel, all integrated with a single 12-bit analog-to-digital Table 1. Related Devices converter (ADC). Part No. Description Each channel features a gain range of 16 dB to 34 dB in 6 dB AD8285 4-Channel LNA/PGA/AAF, pseudosimultaneous increments and an ADC with a conversion rate of up to 72 MSPS. channel sampling with ADC The combined input-referred noise voltage of the entire channel AD8284 4-Channel LNA/PGA/AAF, sequential channel is 3.5 nV/Hz at maximum gain. The channel is optimized for sampling with ADC dynamic performance and low power in applications where a ADA8282 4-Channel LNA/PGA small package size is critical. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112015 Analog Devices, Inc. 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ZSEL CS SCLK AVDD18x SDIO AVDD33x PDWN AUX MUXA DVDD18x CLK+ CLK DVDD33x VREF RBIAS 09795-001AD8283 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Clock Jitter Considerations .................................................. 17 Applications...............................................................................1 SDIO Pin ............................................................................. 17 Functional Block Diagram .........................................................1 SCLK Pin ............................................................................. 17 General Description ..................................................................1 CS Pin .................................................................................. 17 Revision History ........................................................................2 RBIAS Pin............................................................................ 17 Specifications .............................................................................3 Voltage Reference ................................................................ 17 AC Specifications ...................................................................3 Power and Ground Recommendations ................................ 18 Digital Specifications .............................................................5 Exposed Paddle Thermal Heat Slug Recommendations ...... 18 Switching Specifications.........................................................6 Serial Peripheral Interface (SPI) .............................................. 19 Absolute Maximum Ratings ......................................................7 Hardware Interface .............................................................. 19 ESD Caution ..........................................................................7 Memory Map........................................................................... 21 Pin Configuration and Function Descriptions...........................8 Reading the Memory Map Table.......................................... 21 Typical Performance Characteristics .......................................10 Logic Levels ......................................................................... 21 Theory of Operation ................................................................14 Reserved Locations .............................................................. 21 Radar Receive Path AFE ......................................................14 Default Values...................................................................... 21 Channel Overview ...............................................................15 Application Diagrams.............................................................. 25 ADC.....................................................................................16 Outline Dimensions ................................................................ 27 Clock Input Considerations .................................................16 Ordering Guide ................................................................... 27 Clock Duty Cycle Considerations ........................................17 Automotive Products ........................................................... 27 REVISION HISTORY 8/15Rev. B to Rev. C Changed AD951x/AD952x to AD9515/AD9520-0 ... Throughout Added Table 1 Renumbered Sequentially .................................1 10/14Rev. A to Rev. B Changes to Addr. (Hex) 0x15, Table 8......................................23 Changes to Ordering Guide .....................................................27 11/13Rev. 0 to Rev. A Changed Maximum f from 80 MSPS to 72 MSPS SAMPLE ................................................................................. Throughout Changed Clock Pulse Width High/Low (t /t ) at 72 MSPS EH EL from 6.25 ns to 6.94ns Table 3...................................................6 Changes to Figure 25 ...............................................................14 Changes to Register Address 10 Bits 5:0 and Register Address 0x12, Bit 3 Table 8 .....................................................23 Updated Outline Dimensions ..................................................27 4/11Revision 0: Initial Version Rev. C Page 2 of 27