Radar Receive Path AFE: 4-Channel Mux with LNA, PGA, AAF, and ADC Data Sheet AD8284 FEATURES FUNCTIONAL BLOCK DIAGRAM 4-channel mux to LNA, PGA, AAF 1 direct-to-ADC channel Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) REFERENCE SPI-programmable gain = 17 dB to 35 dB in 6 dB steps INA+ Antialiasing filter (AAF) AD8284 INA Programmable third-order low-pass elliptic filter (LPF) from SATURATION DETECTION 9 MHz to 15 MHz INB+ Analog-to-digital converter (ADC) INB 12 bits of accuracy of up to 60 MSPS MUX LNA PGA AAF INC+ SNR = 67 dB INC SFDR = 68 dBc D0 12-BIT MUX TO Low power, 345 mW at 12 bits per 60 MSPS IND+ ADC D11 IND Low noise, 3.5 nV/Hz maximum of input referred voltage noise INADC+ Power-down mode INADC 64-lead, 10 mm 10 mm TQFP package Specified from 40C to +105C SPI Qualified for automotive applications APPLICATIONS Automotive radar Adaptive cruise control Figure 1. Collision avoidance Blind spot detection Self parking Electronic bumper GENERAL DESCRIPTION The AD8284 is an integrated analog front end designed for low for dynamic performance and low power in applications where cost, compact size, flexibility, and ease of use. It contains a a small package size is critical. 4-channel differential multiplexer (mux), a 1-channel low noise Fabricated in an advanced CMOS process, the AD8284 is available preamplifier (LNA) with a programmable gain amplifier (PGA) in a 10 mm 10 mm, RoHS compliant, 64-lead TQFP. It is speci- and an antialiasing filter (AAF), as well as one direct-to-ADC fied over the automotive temperature range of 40C to +105C. channel, all integrated with a single, 12-bit analog-to-digital converter (ADC). The AD8284 also incorporates a saturation Table 1. Related Devices detection circuit for high frequency overvoltage conditions that Part No. Description would otherwise be filtered by the AAF. AD8285 4-Channel LNA/PGA/AAF, pseudosimultaneous channel sampling with ADC The analog channel features a gain range of 17 dB to 35 dB in AD8283 6-Channel LNA/PGA/AAF, pseudosimultaneous 6 dB increments, and an ADC with a conversion rate of up to channel sampling with ADC 60 MSPS. The combined input referred voltage noise of the entire ADA8282 4-Channel LNA/PGA channel is 3.5 nV/Hz at maximum gain. The channel is optimized Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com ZSEL CS MUX 1 TO MUX 0 SCLK AVDD18 SDI AVDD33 SDO PDWN SFLAG DVDD18 DVDD33x AUX VREF CLK+ RBIAS CLK 10992-001AD8284 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Jitter Considerations ....................................................... 16 Applications ....................................................................................... 1 SDI and SDO Pins ...................................................................... 16 Functional Block Diagram .............................................................. 1 SCLK Pin ..................................................................................... 16 General Description ......................................................................... 1 CS Pin........................................................................................... 16 Revision History ............................................................................... 2 RBIAS Pin .................................................................................... 16 Specifications ..................................................................................... 3 Voltage Reference ....................................................................... 16 AC Specifications .......................................................................... 3 Power and Ground Recommendations ................................... 16 Digital Specifications ................................................................... 5 Exposed Pad Thermal Heat Slug Recommendations ............ 17 Switching Specifications .............................................................. 6 Serial Port Interface (SPI) .............................................................. 18 Absolute Maximum Ratings ....................................................... 7 Hardware Interface ..................................................................... 18 ESD Caution .................................................................................. 7 Memory Map .................................................................................. 20 Pin Configuration and Function Descriptions ............................. 8 Reading the Memory Map Table .............................................. 20 Typical Performance Characteristics ........................................... 10 Logic Levels ................................................................................. 20 Theory of Operation ...................................................................... 12 Reserved Locations .................................................................... 20 Radar Receive Path AFE ............................................................ 12 Default Values ............................................................................. 20 Channel Overview ...................................................................... 13 Application Circuits ....................................................................... 24 ADC ............................................................................................. 15 Packaging and Ordering Information ......................................... 26 AUX Channel .............................................................................. 15 Outline Dimensions ................................................................... 26 Clock Input Considerations ...................................................... 15 Ordering Guide .......................................................................... 26 Clock Duty Cycle Considerations ............................................ 16 Automotive Products ................................................................. 26 REVISION HISTORY 8/15Rev. C to Rev. D Changed AD951x/AD952x to AD9515/AD9520-0 .... Throughout Added Table 1 Renumbered Sequentially .................................... 1 6/14Rev. B to Rev. C Changed 80 MSPS to 60 MSPS .................................... Throughout Changes to Table 1 ............................................................................ 3 Changed 6.25 to 8.33, Clock Pulse Width High Parameter, Clock Pulse Width Low Parameter, and Data Setup Time Parameter, Table 3 ............................................................................. 6 7/13Rev. A to Rev. B Changes to Input Resistance and Power-Down Dissipation Parameters Table 1 ........................................................................... 3 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 1/13Rev. 0 to Rev. A Changes to Figure 16 ...................................................................... 14 10/12Revision 0: Initial Version Rev. D Page 2 of 28