Radar Receive Path AFE: 4-Channel LNA/PGA/AAF with ADC Data Sheet AD8285 FEATURES FUNCTIONAL BLOCK DIAGRAM 4-channel LNA, PGA, and AAF 1 direct to ADC channel Programmable gain amplifier (PGA) INA+ REFERENCE Includes low noise preamplifier (LNA) LNA PGA AAF INA Serial peripheral interface (SPI) programmable gain INB+ 16 dB to 34 dB in 6 dB steps LNA PGA AAF INB Antialiasing filter (AAF) DSYNC MUX INC+ LNA PGA AAF Programmable third order, low-pass elliptic filter (LPF) INC 12-BIT D 0:11 DRV ADC from 1.0 MHz to 12.0 MHz IND+ LNA PGA AAF IND Analog-to-digital converter (ADC) INADC+ 12 bits of accuracy up to 72 MSPS INADC Signal-to-noise ratio (SNR): 68.5 dB SPI Spurious-free dynamic range (SFDR): 68 dB at gain = 16 dB AD8285 Low power: 185 mW per channel at 12 bits and 72 MSPS Low noise: 3.5 nV/Hz maximum of input referred voltage noise Power-down mode NOTES 1. AVDD18x = AVDD18, AVDD18ADC. 72-lead, 10 mm 10 mm LFCSP package AVDD33x = AVDD33, AVDD33A, AVDD33B, AVDD33C, AVDD33D, AVDD33REF. DVDD18x = DVDD18, DVDD18CLK. DVDD33x = DVDD33, DVDD33SPI, DVDD33CLK, DVDD33DRV. Specified from 40C to +105C Figure 1. Qualified for automotive applications APPLICATIONS Automotive radar Adaptive cruise control Collision avoidance Blind spot detection Self parking Electronic bumper GENERAL DESCRIPTION The AD8285 is designed for low cost, low power, compact size, Fabricated in an advanced complementary metal oxide flexibility, and ease of use. It contains four channels of a low noise semiconductor (CMOS) process, the AD8285 is available in a preamplifier (LNA) with a programmable gain amplifier (PGA) 10 mm 10 mm, RoHS compliant, 72-lead LFCSP that is specified and an antialiasing filter (AAF) plus one direct to ADC channel, all over the automotive temperature range of 40C to +105C. integrated with a single 12-bit analog-to-digital converter (ADC). Table 1. Related Devices Each channel features a gain range of 16 dB to 34 dB in 6 dB Part No. Description increments and an ADC with a conversion rate of up to 72 MSPS. AD8283 6-channel LNA/PGA/AAF, pseudo simultaneous The combined input referred noise voltage of the entire channel channel sampling with ADC is 3.5 nV/Hz at maximum gain. The channel is optimized for AD8284 4-channel LNA/PGA/AAF, sequential channel dynamic performance and low power in applications where a sampling with ADC small package size is critical. ADA8282 4-channel LNA/PGA Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20142015 Analog Devices, Inc. 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ZSEL CS SCLK AVDD18x SDIO AVDD33x PDWN AUX MUXA DVDD18x CLK+ CLK DVDD33x VREF RBIAS 11952-001AD8285 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SDIO Pin ...................................................................................... 17 Applications ....................................................................................... 1 SCLK Pin ..................................................................................... 17 Functional Block Diagram .............................................................. 1 CS Pin .......................................................................................... 17 General Description ......................................................................... 1 RBIAS Pin .................................................................................... 17 Revision History ............................................................................... 2 Voltage Reference ....................................................................... 18 Specif icat ions ..................................................................................... 3 Power and Ground Recommendations ................................... 18 AC Specifications .......................................................................... 3 Exposed Paddle Thermal Heat Slug Recommendations ...... 18 Digital Specifications ................................................................... 5 Serial Peripheral Interface (SPI) ................................................... 19 Switching Specifications .............................................................. 6 Hardware Interface ..................................................................... 19 Absolute Maximum Ratings ............................................................ 7 Memory Map .................................................................................. 21 ESD Caution .................................................................................. 7 Reading the Memory Map Table .............................................. 21 Pin Configuration and Function Descriptions ............................. 8 Logic Levels ................................................................................. 21 Typical Performance Characteristics ........................................... 10 Reserved Locations .................................................................... 21 Theory of Operation ...................................................................... 14 Default Values ............................................................................. 21 Radar Receive Path AFE ............................................................ 14 Application Diagrams .................................................................... 25 Channel Overview ...................................................................... 15 Outline Dimensions ....................................................................... 27 ADC ............................................................................................. 16 Ordering Guide .......................................................................... 27 Clock Input Considerations ...................................................... 16 Automotive Products ................................................................. 27 Clock Duty Cycle Considerations ............................................ 17 Clock Jitter Considerations ....................................................... 17 REVISION HISTORY 9/15Rev. A to Rev. B Added Table 1 Renumbered Sequentially .................................... 1 10/14Rev. 0 to Rev. A Changes to Addr. (Hex) 0x15, Table 8 ......................................... 23 Changes to Ordering Guide .......................................................... 27 5/14Revision 0: Initial Version Rev. B Page 2 of 27