160 dB Range (100 pA 10 mA) a Logarithmic Converter AD8304 FEATURES FUNCTIONAL BLOCK DIAGRAM Optimized for Fiber Optic Photodiode Interfacing VPS2 PWDN VPS1 Eight Full Decades of Range 10 2 12 Law Conformance 0.1 dB from 1 nA to 1 mA AD8304 Single-Supply Operation (3.0 V 5.5 V) PDB BIAS VREF 7 VREF Complete and Temperature Stable VPDB 6 Accurate Laser-Trimmed Scaling: ~10k 0.5V VSUM Logarithmic Slope of 10 mV/dB (at VLOG Pin) 3 I 8 Basic Logarithmic Intercept at 100 pA VLOG PD INPT 4 Easy Adjustment of Slope and Intercept 9 BFIN 5k TEMPERATURE 5 Output Bandwidth of 10 MHz, 15 V/ s Slew Rate VSUM COMPENSATION 13 BFNG 1-, 2-, or 3-Pole Low-Pass Filtering at Output Miniature 14-Lead Package (TSSOP) Low Power: ~4.5 mA Quiescent Current (Enabled) 1 14 11 APPLICATIONS VNEG ACOM VOUT High Accuracy Optical Power Measurement Wide Range Baseband Log Compression Versatile Detector for APC Loops PRODUCT DESCRIPTION The default value of the logarithmic slope at the output VLOG is The AD8304 is a monolithic logarithmic detector optimized for accurately scaled to 10 mV/dB (200 mV/decade). The resistance the measurement of low frequency signal power in fiber optic at this output is laser-trimmed to 5 k , allowing the slope to be systems. It uses an advanced translinear technique to provide an lowered by shunting it with an external resistance the addition exceptionally large dynamic range in a versatile and easily used of a capacitor at this pin provides a simple low-pass filter. The form. Its wide measurement range and accuracy are achieved intermediate voltage VLOG is buffered in an output stage that can using proprietary design techniques and precise laser trimming. swing to within about 100 mV of ground (or V ) and the posi- N In most applications only a single positive supply, V , of 5 V tive supply, V , and provides a peak current drive capacity of P P will be required, but 3.0 V to 5.5 V can be used, and certain 20 mA. The slope can be increased using the buffer and a pair applications benefit from the added use of a negative supply, of external feedback resistors. An accurate voltage reference of V . When using low supply voltages, the log slope is readily 2V is also provided to facilitate the repositioning of the intercept. N altered to fit the available span. The low quiescent current and Many operational modes are possible. For example, low-pass filters chip disable features facilitate use in battery-operated applications. of up to three poles may be implemented, to reduce the output The input current, I , flows in the collector of an optimally noise at low input currents. The buffer may also serve as a com- PD scaled NPN transistor, connected in a feedback path around a parator, with or without hysteresis, using the 2 V reference, for low offset JFET amplifier. The current-summing input node example, in alarm applications. The incremental bandwidth of operates at a constant voltage, independent of current, with a a translinear logarithmic amplifier inherently diminishes for small default value of 0.5 V this may be adjusted over a wide range, input currents. At the 1 nA level, the AD8304s bandwidth is including ground or below, using an optional negative supply. about 2 kHz, but this increases in proportion to I up to a PD An adaptive biasing scheme is provided for reducing the dark maximum value of 10 MHz. current at very low light input levels. The voltage at Pin VPDB The AD8304 is available in a 14-lead TSSOP package and specified applies approximately 0.1 V across the diode for I = 100 pA, PD for operation from 40C to +85C. rising linearly with current to 2.0 V of net bias at I = 10 mA. PD The input pin INPT is flanked by the guard pins VSUM that track the voltage at the summing node to minimize leakage. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax: 781/326-8703 Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices.AD8304SPECIFICATIONS (V = 5 V, V = 0 V, T = 25 C, unless otherwise noted.) P N A 1 1 Parameter Conditions Min Typ Max Unit INPUT INTERFACE Pin 4, INPT Pin 3 and Pin 5, VSUM Specified Current Range Flows toward INPT Pin 100 pA 10 mA Input Node Voltage Internally preset may be altered 0.46 0.5 0.54 V Temperature Drift 40C < T < +85C 0.02 mV/C A Input Guard Offset Voltage V V 20 +20 mV IN SUM 2 PHOTODIODE BIAS Established between Pin 6, V , and Pin 4 PDB Minimum Value I = 100 pA 70 100 mV PD Transresistance 200 mV/mA LOGARITHMIC OUTPUT Pin 8, VLOG Slope Laser-trimmed at 25C 196 200 204 mV/dec < 70C 194 207 mV/dec 0C < T A Intercept Laser-trimmed at 25C60 100 140 pA 0C < T < 70C35 175 pA A < 1 mA, Peak Error 0.05 0.25 dB Law Conformance Error 10 nA < I PD 1 nA < I < 1 mA, Peak Error 0.1 0.7 dB PD Maximum Output Voltage 1.6 V = 0 V 0.1 V Minimum Output Voltage Limited by V N Output Resistance Laser-trimmed at 25C 4.95 5 5.05 k REFERENCE OUTPUT Pin 7, VREF Voltage WRT Ground Laser-trimmed at 25C 1.98 2 2.02 V 40C < T < +85C 1.92 2.08 V A Output Resistance 2 OUTPUT BUFFER Pin 9, BFIN Pin 13, BFNG Pin 11, VOUT Input Offset Voltage 20 +20 mV Input Bias Current Flowing out of Pin 9 or Pin 13 0.4 A Incremental Input Resistance 35 M Output Range R = 1 k to ground V 0.1 V L P Output Resistance 0.5 3 Wide-Band Noise I > 1 A (see Typical Performance Characteristics) 1 V/Hz PD 3 Small Signal Bandwidth I > 1 A (see Typical Performance Characteristics) 10 MHz PD Slew Rate 0.2 V to 4.8 V output swing 15 V/s POWER-DOWN INPUT Pin 2, PWDN Logic Level, HI State 40C < T < +85C, 2.7 V < V < 5.5 V 2 V A P Logic Level, LO State 40C < T < +85C, 2.7 V < V < 5.5 V 1 V A P POWER SUPPLY Pin 10 and Pin 12, VPS1 and VPS2 Pin 1, VNEG Positive Supply Voltage 3.0 5 5.5 V Quiescent Current 4.5 5.3 mA In Disabled State 60 A 4 Negative Supply Voltage 1V V < 8V 0 5.5 V P N NOTES 1 Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 2 This bias is internally arranged to track the input voltage at INPT it is not specified relative to ground. 3 Output Noise and Incremental Bandwidth are functions of Input Current see Typical Performance Characteristics. 4 Optional Specications subject to change without notice. 2 REV. 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