Fast, Voltage-Out, DC to 440 MHz, 95 dB Logarithmic Amplifier AD8310 FEATURES FUNCTIONAL BLOCK DIAGRAM Multistage demodulating logarithmic amplifier AD8310 VPOS ENBL Voltage output, rise time <15 ns BAND GAP REFERENCE 8mA SUPPLY 5 7 ENABLE AND BIASING High current capacity: 25 mA into grounded R L SIX 14.3dB 900MHz BFIN BUFFER 6 AMPLIFIER STAGES 95 dB dynamic range: 91 dBV to +4 dBV INHI INPUT +INPUT 8 1.0k Single supply of 2.7 V min at 8 mA typ MIRROR INPUT 1 INLO 2 A + VOUT DC to 440 MHz operation, 0.4 dB linearity 3 /dB 4 OUTPUT 2 Slope of +24 mV/dB, intercept of 108 dBV 3k 3k NINE DETECTOR CELLS SPACED 14.3dB Highly stable scaling over temperature COMM 1k 2 COMMON COMM Fully differential dc-coupled signal path COMM OFLT OFFSET INPUT-OFFSET 3 FILTER 100 ns power-up time, 1 mA sleep current COMPENSATION LOOP 33pF COMM APPLICATIONS Figure 1. Conversion of signal level to decibel form Transmitter antenna power measurement Receiver signal strength indication (RSSI) Low cost radar and sonar signal processing Network and spectrum analyzers Signal-level determination down to 20 Hz True-decibel ac mode for multimeters GENERAL DESCRIPTION The fully differential input offers a moderately high impedance (1 k in parallel with about 1 pF). A simple network can match The AD8310 is a complete, dc to 440 MHz demodulating the input to 50 and provide a power sensitivity of 78 dBm to logarithmic amplifier (log amp) with a very fast voltage mode +17 dBm. The logarithmic linearity is typically within 0.4 dB output, capable of driving up to 25 mA into a grounded load in up to 100 MHz over the central portion of the range, but it is under 15 ns. It uses the progressive compression (successive somewhat greater at 440 MHz. There is no minimum frequency detection) technique to provide a dynamic range of up to 95 dB limit the AD8310 can be used down to low audio frequencies. to 3 dB law conformance or 90 dB to a 1 dB error bound up Special filtering features are provided to support this wide range. to 100 MHz. It is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of The output voltage runs from a noise-limited lower boundary of 2.7 V to 5.5 V at 8 mA is needed, corresponding to a power 400 mV to an upper limit within 200 mV of the supply voltage consumption of only 24 mW at 3 V. A fast-acting CMOS- for light loads. The slope and intercept can be readily altered compatible enable pin is provided. using external resistors. The output is tolerant of a wide variety of load conditions and is stable with capacitive loads of 100 pF. Each of the six cascaded amplifier/limiter cells has a small- signal gain of 14.3 dB, with a 3 dB bandwidth of 900 MHz. The AD8310 provides a unique combination of low cost, small A total of nine detector cells are used to provide a dynamic size, low power consumption, high accuracy and stability, high range that extends from 91 dBV (where 0 dBV is defined as dynamic range, a frequency range encompassing audio to UHF, the amplitude of a 1 V rms sine wave), an amplitude of about fast response time, and good load-driving capabilities, making 40 V, up to +4 dBV (or 2.2 V). The demodulated output this product useful in numerous applications that require the is accurately scaled, with a log slope of 24 mV/dB and an reduction of a signal to its decibel equivalent. intercept of 108 dBV. The scaling parameters are supply- and temperature-independent. The AD8310 is available in the industrial temperature range of 40C to +85C in an 8-lead MSOP package. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01084-001AD8310 TABLE OF CONTENTS Features .............................................................................................. 1 Using the AD8310 .......................................................................... 14 Applications ....................................................................................... 1 Basic Connections ...................................................................... 14 Functional Block Diagram .............................................................. 1 Transfer Function in Terms of Slope and Intercept ............... 15 General Description ......................................................................... 1 dBV vs. dBm ............................................................................... 15 Revision History ............................................................................... 2 Input Matching ........................................................................... 15 Specif icat ions ..................................................................................... 3 Narrow-Band Matching ............................................................ 16 Absolute Maximum Ratings ............................................................ 4 General Matching Procedure .................................................... 16 ESD Caution .................................................................................. 4 Slope and Intercept Adjustments ............................................. 17 Pin Configuration and Function Descriptions ............................. 5 Increasing the Slope to a Fixed Value ...................................... 17 Typical Performance Characteristics ............................................. 6 Output Filtering .......................................................................... 18 Theory of Operation ........................................................................ 9 Lowering the High-Pass Corner Frequency of the Offset Compensation Loop .................................................................. 18 Progressive Compression ............................................................ 9 Applications Information .............................................................. 19 Slope and Intercept Calibration ................................................ 10 Cable-Driving ............................................................................. 19 Offset Control ............................................................................. 10 DC-Coupled Input ..................................................................... 19 Product Overview ........................................................................... 11 Evaluation Board ............................................................................ 20 Enable Interface .......................................................................... 11 Die Information .............................................................................. 22 Input Interface ............................................................................ 11 Outline Dimensions ....................................................................... 23 Offset Interface ........................................................................... 12 Ordering Guide .......................................................................... 23 Output Interface ......................................................................... 12 REVISION HISTORY 6/10Rev. E to Rev. F 7/03Rev. B to Rev. C Added Die Information Section ................................................... 22 Replaced TPC 12 ............................................................................... 5 Updated Outline Dimensions ....................................................... 23 Change to DC-Coupled Input Section ........................................ 14 Changes to Ordering Guide .......................................................... 23 Replaced Figure 20 ......................................................................... 15 Updated Outline Dimensions ....................................................... 16 6/05Rev. D to Rev. E Changes to Figure 6 .......................................................................... 6 2/03Rev. A to Rev. B Change to Basic Connections Section ......................................... 14 Change to Evaluation Board Section ........................................... 15 Changes to Equation 10 ................................................................. 17 Change to Table III ......................................................................... 16 Changes to Ordering Guide .......................................................... 22 Updated Outline Dimensions ....................................................... 16 10/04Rev. C to Rev. D 1/00Rev. 0 to Rev. A Format Updated .................................................................. Universal 10/99Revision 0: Initial Version Typical Performance Characteristics Reordered .......................... 6 Changes to Figure 41 and Figure 42 ............................................. 20 Rev. F Page 2 of 24