DC to 600 MHz, Dual-Digital Variable Gain Amplifiers Data Sheet AD8366 FEATURES FUNCTIONAL BLOCK DIAGRAM Matched pair of differential, digitally controlled VGAs Gain range: 4.5 dB to 20.25 dB 0.25 dB gain step size Operating frequency VPSIA BIT0/CS DC to 150 MHz (2 V p-p) 3 dB bandwidth: 600 MHz IPPA BIT1/SDAT Noise figure (NF) IPMA BIT2/SCLK 11.4 dB at 10 MHz at maximum gain ENBL BIT3 18 dB at 10 MHz at minimum gain DIGITAL GAIN CONTROL LOGIC ICOM OCOM OIP3: 45 dBm at 10 MHz HD2/HD3 IPMB BIT4 Better than 90 dBc for 2 V p-p output at 10 MHz at IPPB BIT 5 maximum gain VPSIB DENA Differential input and output Adjustable output common-mode Optional dc output offset correction Serial/parallel mode gain control Power-down feature Figure 1. Single 5 V supply operation APPLICATIONS Baseband I/Q receivers Diversity receivers Wideband ADC drivers GENERAL DESCRIPTION The AD8366 is a matched pair of fully differential, low noise and The output common-mode voltage defaults to VPOS/2 but can low distortion, digitally programmable variable gain amplifiers be programmed via the VCMA and VCMB pins over a range (VGAs). The gain of each amplifier can be programmed separately of voltages. The input common-mode voltage also defaults or simultaneously over a range of 4.5 dB to 20.25 dB in steps of to VPOS/2 but can be driven down to 1.5 V. A built-in, dc offset 0.25 dB. The amplifier offers flat frequency performance from dc compensation loop can be used to eliminate dc offsets from prior to 70 MHz, independent of gain code. stages in the signal chain. This loop can also be disabled if dc- coupled operation is desired. The AD8366 offers excellent spurious-free dynamic range, suitable for driving high resolution analog-to-digital converters (ADCs). The digital interface allows for parallel or serial mode gain The NF at maximum gain is 11.4 dB at 10 MHz and increases programming. The AD8366 operates from a 4.75 V to 5.25 V ~2 dB for every 4 dB decrease in gain. Over the entire gain range, supply and consumes typically 180 mA. When disabled, the the HD3/HD2 are better than 90 dBc for 2 V p-p at the output at part consumes roughly 3 mA. The AD8366 is fabricated using 10 MHz into 200 . The two-tone intermodulation distortion of Analog Devices, Inc., advanced silicon-germanium bipolar 90 dBc into 200 translates to an OIP3 of 45 dBm (38 dBVrms). process, and it is available in a 32-lead exposed paddle LFCSP The differential input impedance of 200 provides a well-defined package. Performance is specified over the 40C to +85C termination. The differential output has a low impedance of ~25 . temperature range. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DECB DECA OFSB OFSA CCMB CCMA VCMB VCMA VPSOB VPSOA OPPB OPPA OPMB OPMA DENB SENB 07584-001AD8366 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Differential Offset Correction .................................... 15 Applications ....................................................................................... 1 Output Common-Mode Control ............................................. 15 Functional Block Diagram .............................................................. 1 Gain Control Interface ............................................................... 16 General Description ......................................................................... 1 Applications Information .............................................................. 17 Revision History ............................................................................... 2 Basic Connections ...................................................................... 17 Specif icat ions ..................................................................................... 3 Direct Conversion Receiver Design ......................................... 18 Parallel and Serial Interface timing ............................................ 5 Quadrature Errors and Image Rejection ................................. 18 Absolute Maximum Ratings ............................................................ 6 Low Frequency IMD3 Performance ........................................ 19 ESD Caution .................................................................................. 6 Baseband Interface ..................................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Characterization Setups ................................................................. 22 Typical Performance Characteristics ............................................. 8 Evaluation Board ............................................................................ 25 Circuit Description ......................................................................... 15 Outline Dimensions ....................................................................... 28 Inputs ........................................................................................... 15 Ordering Guide .......................................................................... 28 Outputs ........................................................................................ 15 REVISION HISTORY 8/2017Rev. A to Rev. B Change to Figure 4 ........................................................................... 7 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 3/2011Rev. 0 to Rev. A Changes to Table 2, Internal Power Dissipation Value ................ 6 10/2010Revision 0: Initial Version Rev. B Page 2 of 28