41 dB Range, 1 dB Step Size, Programmable Dual VGA Data Sheet AD8372 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual independent digitally controlled VGA ENB1 REF1 AD8372 Differential input and output IPC1 OPC1 150 differential input INC1 ONC1 Open-collector differential output CHANNEL 1 POSTAMP RXT1 7.8 dB noise figure to 100 MHz maximum gain CLK2 CLK1 HD2/HD3 better than 77 dBc for 1 V p-p differential output REGISTERS SDO1 SDO2 AND 3 dB bandwidth of 130 MHz SDI1 SDI2 GAIN DECODER 41 dB gain range LCH1 LCH2 1 dB step size 0.2 dB RXT2 Serial 8-bit bidirectional SPI control interface OPC2 IPC2 Wide input dynamic range INC2 ONC2 Pin-programmable output stage CHANNEL 2 POSTAMP ENB2 REF2 Power-down feature Figure 1. Single 5 V supply: 106 mA per channel 32-lead LFCSP, 5 mm 5 mm package APPLICATIONS Differential ADC drivers CMTS upstream direct sampling receivers CATV modem signal scaling Generic RF/IF gain stages Single-ended-to-differential conversion GENERAL DESCRIPTION The AD8372 is a dual, digitally controlled, variable gain setting resistors can be adjusted to manipulate the gain and amplifier (VGA) that provides precise gain control, high IP3, distortion performance of each channel. This is a flexible and low noise figure. The excellent distortion performance and feature in applications where it is desirable to trade off distortion moderate signal bandwidth make the AD8372 a suitable performance for lower power consumption. gain control device for a variety of multichannel receiver The AD8372 is powered on by applying the appropriate logic applications. level to the ENB1, ENB2 pins. When powered down, the AD8372 For wide input dynamic range applications, the AD8372 consumes less than 2.6 mA and offers excellent input-to-output provides a broad 41 dB gain range. The gain is programmed isolation. The gain setting is preserved when powered down. through a bidirectional 4-pin serial interface. The serial inter- Fabricated on an Analog Devices, Inc., high frequency BiCMOS face consists of a clock, latch, data input, and data output lines process, the AD8372 provides precise gain adjustment capabilities for each channel. with good distortion performance. The quiescent current of the The AD8372 provides the ability to set the transconductance of AD8372 is typically 106 mA per channel. The AD8372 amplifier the output stage using a single external resistor. The RXT1 and comes in a compact, thermally enhanced 5 mm 5 mm 32-lead RXT2 pins provide a band gap derived stable reference voltage LFCSP package and operates over the temperature range of of 1.56 V. Typically 2.0 k shunt resistors to ground are used to 40C to +85C. set the maximum gain to a nominal value of 31 dB. The current Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07051-001AD8372 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 10 Functional Block Diagram .............................................................. 1 Single-Ended and Differential Signals ..................................... 10 General Description ......................................................................... 1 Passive Filter Techniques ........................................................... 10 Revision History ............................................................................... 2 Digital Gain Control .................................................................. 10 Specifications ..................................................................................... 3 Driving Analog-to-Digital Converters .................................... 10 Serial Control Interface Timing ................................................. 5 Evaluation Board Schematic ......................................................... 12 Absolute Maximum Ratings ............................................................ 6 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 13 Pin Configuration and Function Descriptions ............................. 7 REVISION HISTORY 9/2017Rev. B to Rev. C Changed CP-32-2 to CP-32-7 ...................................... Throughout Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 6/2011Rev. A to Rev. B Changes to Table 4 ............................................................................ 6 Changes to Figure 4 and Table 5 ..................................................... 7 Added Exposed Pad Notation to Outline Dimensions ............. 13 Changes to Ordering Guide .......................................................... 13 5/2008Rev. 0 to Rev. A Changes to Features and Figure 1 ................................................... 1 Changes to Figure 2 and Figure 3 ................................................... 5 Changes to Figure 9 .......................................................................... 8 Changes to Figure 16 ...................................................................... 12 11/2007Revision 0: Initial Version Rev. C Page 2 of 16