Ultralow Distortion IF Dual VGA Data Sheet AD8376 FEATURES FUNCTIONAL BLOCK DIAGRAM A4 A3 A2 A1 A0 VCCA GNDA Dual independent digitally controlled VGAs Bandwidth of 700 MHz (3 dB) CHANNEL A GAIN Gain range: 4 dB to +20 dB AD8376 DECODER Step size: 1 dB 0.2 dB OPA+ Differential input and output IPA+ OPA+ Noise figure: 8.7 dB maximum gain POST-AMP Output IP3 of ~50 dBm at 200 MHz IPA OPA Output P1dB of 20 dBm at 200 MHz OPA VCMA ENBA Dual parallel 5-bit control interface ENBB Provides constant SFDR vs. gain VCMB OPB+ Power-down control IPB+ OPB+ Single 5 V supply operation POST-AMP 32-lead, 5 mm x 5 mm LFCSP OPB IPB OPB APPLICATIONS CHANNEL B Differential ADC drivers GAIN DECODER Main and diversity IF sampling receivers Wideband multichannel receivers B4 B3 B2 B1 B0 VCCB GNDB Instrumentation Figure 1. GENERAL DESCRIPTION The AD8376 is a dual channel, digitally controlled, variable gain AD8376 consumes less than 5 mA and offers excellent input-to- wide bandwidth amplifier that provides precise gain control, output isolation, lower than 50 dB at 200 MHz. high IP3, and low noise figure. The excellent distortion perform- Fabricated on an Analog Devices, Inc., high speed SiGe process, ance and high signal bandwidth make the AD8376 an excellent the AD8376 is supplied in a compact, thermally enhanced, gain control device for a variety of receiver applications. 5 mm 5mm 32-lead LFCSP package and operates over the Using an advanced high speed SiGe process and incorporating temperature range of 40C to +85C. proprietary distortion cancellation techniques, the AD8376 40 65 achieves 50 dBm output IP3 at 200 MHz. 50 60 The AD8376 provides a broad 24 dB gain range with 1 dB resolution. The gain of each channel is adjusted through 60 55 dedicated 5-pin control interfaces and can be driven using OIP3 70 50 standard TTL levels. The open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by 80 45 the loading impedance. Thus, the signal voltage gain is directly HD2 proportional to the load. 90 40 Each channel of the AD8376 can be individually powered on by HD3 100 35 applying the appropriate logic level to the ENBA and ENBB power enable pins. The quiescent current of the AD8376 is 110 30 40 60 80 100 120 140 160 180 200 typically 130 mA per channel. When powered down, the FREQUENCY (MHz) Figure 2. Harmonic Distortion and Output IP3 vs. Frequency Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com HARMONIC DISTORTION (dBc), OUTPUT 2V p-p OIP3 (dBm), OUTPUT 3dBm/TONE 06725-001 06725-052AD8376 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Structure ............................................................................ 12 Applications ....................................................................................... 1 Applications ..................................................................................... 13 Functional Block Diagram .............................................................. 1 Basic Connections ...................................................................... 13 General Description ......................................................................... 1 Single-Ended-to-Differential Conversion ............................... 13 Revision History ............................................................................... 2 Broadband Operation ................................................................ 15 Specifications ..................................................................................... 3 ADC Interfacing ......................................................................... 15 Absolute Maximum Ratings ............................................................ 5 Layout Considerations ............................................................... 18 ESD Caution .................................................................................. 5 Characterization Test Circuits .................................................. 18 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ........................................................................ 19 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 23 Circuit Description ......................................................................... 12 Ordering Guide .......................................................................... 23 REVISION HISTORY 10/13Rev. A to Rev. B Changed ENBA, ENBB, A0 to A4, B0 to B4 Maximum Rating to +0.6 V Table 3 .............................................................................. 5 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 10/10Rev. 0 to Rev. A Changes to Figure 3 and Table 4 ..................................................... 6 Changes to Figure 36 ...................................................................... 14 Added Exposed Pad Notation to Outline Dimensions ............. 23 8/07Revision 0: Initial Version Rev. B Page 2 of 24