Low Cost, Low Power, True RMS-to-DC Converter Data Sheet AD8436 FEATURES FUNCTIONAL BLOCK DIAGRAM CAVG CCF Delivers true rms or average rectified value of ac waveform Fast settling at all input levels VCC AD8436 Accuracy: 10 V 0.25% of reading (B grade) 100k SUM IGND Wide dynamic input range 8k 100k 100 V rms to 3 V rms (8.5 V p-p) full-scale input range RMS CORE RMS VEE Larger inputs with external scaling OGND Wide bandwidth: 16k OUT 1 MHz for 3 dB (300 mV) 10pF 65 kHz for additional 1% error 10k 10k Zero converter dc output offset IBUFGN No residual switching products IBUFIN Specified at 300 mV rms input IBUFOUT IBUFIN+ FET OP AMP Accurate conversion with crest factors up to 10 + Low power: 300 A typical at 2.4 V High-Z FET separately powered input buffer OBUFIN+ + DC BUFFER OBUFOUT 12 16k R 10 , C 2 pF IN IN OBUFIN Precision dc output buffer Wide power supply voltage range Figure 1. Dual: 2.4 V to 18 V single: 4.8 V to 36 V 4 mm 4 mm LFCSP and 8 mm 6 mm QSOP packages ESD protected GENERAL DESCRIPTION The AD8436 is a new generation, translinear precision, low The precision dc output buffer minimizes errors when driving power, true rms-to-dc converter loaded with options. It computes a low impedance loads with extremely low offset voltages, thanks precise dc equivalent of the rms value of ac waveforms, including to internal bias current cancellation. Unlike digital solutions, the complex patterns such as those generated by switch mode power AD8436 has no switching circuitry limiting performance at high or low amplitudes (see Figure 2). A usable response of <100 V supplies and triacs. Its accuracy spans a wide range of input levels (see Figure 2) and temperatures. The ensured accuracy of 0.5% and >3 V extends the dynamic range with no external scaling, and 10 V output offset result from the latest Analog Devices, accommodating demanding low level signal conditions and Inc., technology. The crest factor error is <0.5% for CF values allowing ample overrange without clipping. between 1 and 10. GREATER INPUT DYNAMIC RANGE The AD8436 delivers true rms results at less cost than misleading peak, averaging, or digital solutions. There is no programming AD8436 expense or processor overhead to consider, and the 4 mm 4 mm package easily fits into tight applications. On-board buffer SOLUTION amplifiers enable the widest range of options for any rms-to-dc converter available, regardless of cost. For minimal applications, 100V 1mV 10mV 100mV 1V 3V only a single external averaging capacitor is required. The built-in Figure 2. Usable Dynamic Range of the AD8436 vs. high impedance FET buffer provides an interface for external The AD8436 operates from single or dual supplies of 2.4 V attenuators, frequency compensation, or driving low impedance (4.8 V) to 18 V (36 V). A and J grades are available in a compact loads. A matched pair of internal resistors enables an easily 4 mm 4 mm, 20-lead chip-scale package A and B grades are configurable gain-of-two or more, extending the usable input available in a 20-lead QSOP package. The operating temperature range even lower. The low power, precision input buffer makes ranges are 40C to 125C for A and B grades and 0C to 70C the AD8436 attractive for use in portable multi-meters and for J grade. other battery-powered applications. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 10033-002 10033-001AD8436 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 10 Functional Block Diagram .............................................................. 1 Overview ..................................................................................... 10 General Description ......................................................................... 1 Applications Information .............................................................. 12 Revision History ............................................................................... 2 Using the AD8436 ...................................................................... 12 Specif icat ions ..................................................................................... 3 Additional Information ............................................................. 15 Absolute Maximum Ratings ............................................................ 4 AD8436 Evaluation Board ............................................................ 17 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 20 Pin Configurations and Function Descriptions ........................... 5 Ordering Guide .......................................................................... 21 Typical Performance Characteristics ............................................. 6 Test Circuits ....................................................................................... 9 REVISION HISTORY 7/2012Rev. 0 to Rev. A 3/2017Rev. D to Rev. E Changed CP-20-10 to CP-20-8 .................................... Throughout Added 20-Lead QSOP ....................................................... Universal Changes to Outline Dimensions ................................................... 21 Changes to Features Section and General Description Section .. 1 Changes to Ordering Guide .......................................................... 22 Changes to Table 1 ............................................................................. 3 Changes to Table 2 ............................................................................. 4 10/2015Rev. C to Rev. D Changes to Table 3 and added Figure 4 and added Table 4 Changes to Figure 5 to Figure 8 ...................................................... 6 Renumbered Sequentially ................................................................ 5 Changes to Equation 1 and change to Column One Heading in Table 5 .......................................................................................... 10 7/2015Rev. B to Rev. C Changes to Table 2 ............................................................................ 4 Changes to Averaging Capacitor ConsiderationsRMS Changes to Figure 5 to Figure 7 ...................................................... 6 Accuracy and to Post Conversion Ripple Reduction Filter Changes to Figure 21 ........................................................................ 9 and changes to Figure 27 Caption ................................................ 12 Changes to Using the FET Input Buffer Section ........................ 14 Changes to Figure 30 to Figure 32 ................................................ 13 Changes to Single-Supply Section and Figure 39 ....................... 15 Changes to Using the FET Input Buffer Section and Using the Added Additional Information Section ....................................... 15 Output Buffer Section .................................................................... 14 Changes to Figure 38 and Figure 41 and added Converting Changes to AD8436 Evaluation Board Section and A Word About Using the AD8436 Evaluation Board Section ................... 17 to Rectified Average Value Section .............................................. 15 Added Single-Supply Operation Section ..................................... 17 Changes to Figure 41 ...................................................................... 16 Changes to Ordering Guide .......................................................... 21 Changes to Figure 42 to Figure 46 ................................................ 17 Changes to Figure 47 and Figure 48............................................. 18 1/2013Rev. A to Rev. B Updated Outline Dimensions ....................................................... 19 Added B Grade Throughout ............................................. Universal Changes to Ordering Guide .......................................................... 20 Changes to Figure 1 and changes to General Description .......... 1 7/2011Revision 0: Initial Version Changes to Table 1 ............................................................................ 3 Changes to Figure 3 ......................................................................... 5 Changes to Figure 9 and Figure 10 ................................................. 6 Changes to FET Input Buffer Section .......................................... 11 Changes to Averaging Capacitor ConsiderationsRMS Accuracy Section and changes to Figure 28 ................................ 12 Deleted Capacitor Construction Section added CAVG Capacitor Styles Section ................................................................. 13 Added Converting to Average Rectified Value Section ............. 15 Changes to Figure 41 ...................................................................... 16 Changes to Evaluation Board Section .......................................... 17 Changes to Figure 48 ...................................................................... 19 Changes to Outline Dimensions ................................................... 20 Changes to Ordering Guide .......................................................... 21 Rev. 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