Complete 10-Bit, 20 MSPS, 80 mW a CMOS A/D Converter AD9200 FEATURES A single clock input is used to control all internal conversion CMOS 10-Bit, 20 MSPS Sampling A/D Converter cycles. The digital output data is presented in straight binary Pin-Compatible with AD876 output format. An out-of-range signal (OTR) indicates an over- Power Dissipation: 80 mW (3 V Supply) flow condition which can be used with the most significant bit Operation Between 2.7 V and 5.5 V Supply to determine low or high overflow. Differential Nonlinearity: 0.5 LSB The AD9200 can operate with supply range from 2.7 V to Power-Down (Sleep) Mode 5.5 V, ideally suiting it for low power operation in high speed Three-State Outputs portable applications. Out-of-Range Indicator The AD9200 is specified over the industrial (40 C to +85 C) Built-In Clamp Function (DC Restore) and commercial (0 C to +70 C) temperature ranges. Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT HIGHLIGHTS PRODUCT DESCRIPTION Low Power The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS The AD9200 consumes 80 mW on a 3 V supply (excluding the analog-to-digital converter with an on-chip sample-and-hold reference power). In sleep mode, power is reduced to below amplifier and voltage reference. The AD9200 uses a multistage 5 mW. differential pipeline architecture at 20 MSPS data rates and Very Small Package guarantees no missing codes over the full operating temperature The AD9200 is available in both a 28-lead SSOP and 48-lead range. LQFP packages. The input of the AD9200 has been designed to ease the devel- Pin Compatible with AD876 opment of both imaging and communications systems. The user The AD9200 is pin compatible with the AD876, allowing older can select a variety of input ranges and offsets and can drive the designs to migrate to lower supply voltages. input either single-ended or differentially. 300 MHz On-Board Sample-and-Hold The sample-and-hold (SHA) amplifier is equally suited for both The versatile SHA input can be configured for either single- multiplexed systems that switch full-scale voltage levels in suc- ended or differential inputs. cessive channels and sampling single-channel inputs at frequen- Out-of-Range Indicator cies up to and beyond the Nyquist rate. AC coupled input The OTR output bit indicates when the input signal is beyond signals can be shifted to a predetermined level, with an onboard the AD9200s input range. clamp circuit (AD9200ARS, AD9200KST). The dynamic per- formance is excellent. Built-In Clamp Function Allows dc restoration of video signals with AD9200ARS and The AD9200 has an onboard programmable reference. An AD9200KST. external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP IN CLK AVDD DRVDD STBY SHA SHA GAIN SHA GAIN SHA GAIN SHA GAIN MODE AIN A/D REFTS THREE- A/D D/A A/D D/A A/D D/A A/D D/A REFBS STATE REFTF CORRECTION LOGIC REFBF OTR OUTPUT BUFFERS VREF D9 AD9200 1V REFSENSE (MSB) D0 (LSB) DRVSS AVSS REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (AVDD = +3 V, DRVDD = +3 V, F = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input S AD9200SPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, T to T unless otherwise noted) MIN MAX Parameter Symbol Min Typ Max Units Condition RESOLUTION 10 Bits CONVERSION RATE F 20 MHz S DC ACCURACY Differential Nonlinearity DNL 0.5 1 LSB REFTS = 2.5 V, REFBS = 0.5 V Integral Nonlinearity INL 0.75 2 LSB Offset Error E 0.4 1.2 % FSR ZS Gain Error E 1.4 3.5 % FSR FS REFERENCE VOLTAGES Top Reference Voltage REFTS 1 AVDD V Bottom Reference Voltage REFBS GND AVDD 1 V Differential Reference Voltage 2 V p-p 1 Reference Input Resistance 10 kW REFTS, REFBS: MODE = AVDD 4.2 kW Between REFTF and REFBF: MODE = AVSS ANALOG INPUT Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD Input Capacitance C 1 pF Switched IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Input Bandwidth (3 dB) BW Full Power (0 dB) 300 MHz DC Leakage Current 23 m A Input = FS INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode) 10 25 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V DRVDD 2.7 3 5.5 V Supply Current IAVDD 26.6 33.3 mA AVDD = 3 V, MODE = AVSS Power Consumption P 80 100 mW AVDD = DRVDD = 3 V, MODE = AVSS D Power-Down 4 mW STBY = AVDD, MODE and CLOCK = AVSS Gain Error Power Supply Rejection PSRR 1 % FS DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz 54.5 57 dB f = 10 MHz 54 dB Effective Bits f = 3.58 MHz 9.1 Bits f = 10 MHz 8.6 Bits Signal-to-Noise SNR f = 3.58 MHz 55 57 dB f = 10 MHz 56 dB Total Harmonic Distortion THD f = 3.58 MHz 59 66 dB f = 10 MHz 58 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz 61 69 dB f = 10 MHz 61 dB Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.05 % REV. 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