12-Bit, 6 GSPS/10.25 GSPS, JESD204B, RF Analog-to-Digital Converter Data Sheet AD9213 The AD9213 features a 16-lane JESD204B interface to support FEATURES maximum bandwidth capability. High instantaneous dynamic range NSD The AD9213 achieves dynamic range and linearity performance 155 dBFS/Hz at 10 GSPS with 9 dBFS, 170 MHz input while consuming <4.6 W typical. The device is based on an inter- 153 dBFS/Hz at 10 GSPS with 1 dBFS, 170 MHz input leaved pipeline architecture and features a proprietary calibration SFDR: 70 dBFS at 10 GSPS with 1 dBFS, 1000 MHz input and randomization technique that suppresses interleaving spurious SFDR excluding H2 and H3 (worst other spur): 89 dBFS at artifacts into its noise floor. The linearity performance of the 10 GSPS with 1 dBFS, 1000 MHz input AD9213 is preserved by a combination of on-chip dithering and Low power dissipation: <4.6 W typical at 10 GSPS calibration, which results in excellent spurious-free performance Integrated input buffer (6.5 GHz input bandwidth) over a wide range of input signal conditions. 1.4 V p-p full-scale analog input with R = 50 IN Applications that require less instantaneous bandwidth can benefit Overvoltage protection from the on-chip, digital signal processing (DSP) capability of 16-lane JESD204B output (up to 16 Gbps line rate) the AD9213 that reduces the output data rate along with the Multichip synchronization capable with 1 sample accuracy number of JESD204B lanes required to support the device. The DDC NCO synchronization included DSP path includes a digital downconverter (DDC) with a 48-bit, Integrated DDC numerically controlled oscillator (NCO), followed by an I/Q digital Selectable decimation factors decimator stage that allows selectable decimation rates that are 16 profile settings for fast frequency hopping factors of two or three. For fast frequency hopping applications, the Fast overrange detection for efficient AGC AD9213 NCO supports up to 16 profile settings with a separate On-chip temperature sensor trigger input, allowing wide surveillance frequency coverage at On-chip negative voltage generators a reduced JESD204B lane count. 16 Low CER: <1 10 The AD9213 supports sample accurate multichip synchronization 12 mm 12 mm, 192-ball BGA-ED package that includes synchronization of the NCOs. The AD9213 is GENERAL DESCRIPTION offered in a 192-ball ball grid array (BGA) package and is The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio specified over a junction temperature range of 20C to +115C. frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instan- taneous bandwidth and low conversion error rates (CER). FUNCTIONAL BLOCK DIAGRAM AVDD2 AVDD DVDD JVDD2 JVDD (2.0V) (1.0V) AGND (1.0V) (2.0V) (1.0V) 2 DIGITAL AVNN1 AD9213 GAIN (1.0V) SERDOUTx 0 BUFFER SERDOUTx 1 16 12 VIN P ADC 16 CORE VIN N DIGITAL DOWN SERDOUTx 15 I/Q VCM CONVERTER FD DGND SIGNAL MONITOR SYNCINB x JESD204B CLOCK SUBCLASS 1 DISTRIBUTION SYSREF x CONTROL CLK P TRIG x CLK N GPIO SPI ASSIGNMENT CONTROL SVDD2 (2.0V) CLKVDD LF GPIO 0 TO GPIO 4 SDIO SCLK CSB (1.0V) Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DFORMAT JESD204B SERIALIZER Tx OUTPUTS 15030-001AD9213 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Outputs ............................................................................... 56 General Description ......................................................................... 1 Introduction to the JESD204B Interface ................................. 56 Functional Block Diagram .............................................................. 1 JESD204B Overview .................................................................. 56 Revision History ............................................................................... 3 Functional Overview ................................................................. 57 Specifications ..................................................................................... 4 JESD204B Link Establishment ................................................. 57 AC Specifications .......................................................................... 5 Physical Layer (Driver) Outputs .............................................. 59 Digital Specifications ................................................................... 6 Setting Up the AD9213 Digital Interface ................................ 60 Switching Specifications .............................................................. 7 Latency ............................................................................................. 63 Timing Specifications .................................................................. 8 End to End Total Latency .......................................................... 63 Absolute Maximum Ratings .......................................................... 10 Example Latency Calculations.................................................. 63 Thermal Characteristics ............................................................ 10 LMFC Referenced Latency ........................................................ 63 ESD Caution ................................................................................ 10 Deterministic Latency .................................................................... 65 Pin Configuration and Function Descriptions ........................... 11 Subclass 0 Operation .................................................................. 65 Typical Performance Characteristics ........................................... 14 Subclass 1 Operation .................................................................. 65 AD9213-6G ................................................................................. 14 Multichip Synchronization (MCS) ............................................... 67 AD9213-10G ............................................................................... 20 Averaged SYSREF Mode For MCS ........................................... 67 Equivalent Circuits ......................................................................... 27 Sampled SYSREF Mode ............................................................. 67 Theory of Operation ...................................................................... 30 MCS Averaged SYSREF Mode Setup ....................................... 68 ADC Architecture ...................................................................... 30 Test Modes ....................................................................................... 70 Analog Input Considerations .................................................... 30 JESD204B Test Modes ............................................................... 70 Voltage Reference ....................................................................... 31 Data Link Layer Test Modes ..................................................... 70 Clock Input Considerations ...................................................... 32 Serial Port Interface (SPI) .............................................................. 73 TMU ................................................................................................. 33 Configuration Using the SPI ..................................................... 73 ADC Overrange and Fast Detect .................................................. 34 SPI Accessible Features .............................................................. 73 ADC Overrange .......................................................................... 34 Hardware Interface ..................................................................... 73 Fast Threshold Detection (FD) ................................................. 34 Memory Map .................................................................................. 74 Digital Downconverter (DDC) ..................................................... 35 Reading the Memory Map Register Tables ............................. 74 DDC General Description ........................................................ 35 Applications Information ............................................................ 108 DDC Frequency Translation ..................................................... 37 Startup Sequence ...................................................................... 108 DDC Decimation Filters ............................................................ 44 Changing Sample Clock Frequency Without Power Down 108 DDC Gain Stage ......................................................................... 48 Power Supply Recommendations ........................................... 109 DDC Complex to Real Conversion .......................................... 48 Outline Dimensions ..................................................................... 110 DDC Example Configurations ................................................. 49 Ordering Guide ........................................................................ 110 Signal Monitor ................................................................................ 53 SPORT Over JESD204B ............................................................. 53 Rev. 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