12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9234 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1 SR DVDD DRVDD SPIVDD JESD204B (Subclass 1) coded serial digital outputs (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) 1.5 W total power per channel at 1 GSPS (default settings) BUFFER SFDR VIN+A ADC 12 CORE VINA 79 dBFS at 340 MHz (1 GSPS) DECIMATE BY 2 FD A 85 dBFS at 340 MHz (500 MSPS) 4 SERDOUT0 SERDOUT1 SIGNAL SERDOUT2 SNR MONITOR SERDOUT3 DECIMATE FD B 63.4 dBFS at 340 MHz (A = 1.0 dBFS, 1 GSPS) IN BY 2 12 65.6 dBFS at 340 MHz (A = 1.0 dBFS, 500 MSPS) VIN+B IN ADC CORE VINB ENOB = 10.4 bits at 10 MHz (1 GSPS) BUFFER DNL = 0.16 LSB INL = 0.35 LSB (1 GSPS) FAST V 1P0 DETECT Noise density SYNCINB CLOCK JESD204B GENERATION SUBCLASS 1 151 dBFS/Hz (1 GSPS) AND ADJUST CONTROL SYSREF 150 dBFS/Hz (500 MSPS) CLK+ CLK 2 SIGNAL 1.25 V, 2.5 V, and 3.3 V dc supply operation SPI CONTROL 4 MONITOR PDWN/ STBY 8 Low swing full-scale input AD9234 1.34 V p-p typical (1 GSPS) AGND DRGND DGND SDIO SCLK CSB 1.63 V p-p typical (500 MSPS) Figure 1. No missing codes Internal ADC voltage reference PRODUCT HIGHLIGHTS Flexible termination impedance 1. Low power consumption analog core, 12-bit, 1.0 GSPS dual 400 , 200 , 100 , and 50 differential analog-to-digital converter (ADC) with 1.5 W per channel. 2 GHz usable analog input full power bandwidth 2. Wide full power bandwidth supports IF sampling of signals 95 dB channel isolation/crosstalk up to 2 GHz. Amplitude detect bits for efficient AGC implementation 3. Buffered inputs with programmable input termination Differential clock input eases filter design and implementation. Optional decimate by 2 DDC per channel 4. Flexible serial port interface (SPI) controls various product Differential clock input features and functions to meet specific system requirements. Integer clock divide by 1, 2, 4, or 8 5. Programmable fast overrange detection. Flexible JESD204B lane configurations 6. 9 mm 9 mm 64-lead LFCSP. Small signal dither 7. Pin compatible with the AD9680 14-bit, 1 GSPS/500 MSPS APPLICATIONS dual ADC. Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point to point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142018 Analog Devices, Inc. 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Technical Support www.analog.com FAST DETECT JESD204B HIGH SPEED SERIALIZER + Tx OUTPUTS 12244-001AD9234 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Complex to Real Conversion ......................................... 36 Applications ....................................................................................... 1 Digital Outputs ............................................................................... 37 Functional Block Diagram .............................................................. 1 Introduction to the JESD204B Interface ................................. 37 Product Highlights ........................................................................... 1 JESD204B Overview .................................................................. 37 Revision History ............................................................................... 3 Functional Overview ................................................................. 38 General Description ......................................................................... 4 JESD204B Link Establishment ................................................. 39 Specifications ..................................................................................... 5 Physical Layer (Driver) Outputs .............................................. 41 DC Specifications ......................................................................... 5 Configuring the JESD204B Link .............................................. 43 AC Specifications .......................................................................... 6 Deterministic Latency .................................................................... 46 Digital Specifications ................................................................... 8 Subclass 0 Operation .................................................................. 46 Switching Specifications .............................................................. 9 Subclass 1 Operation .................................................................. 46 Timing Specifications .................................................................. 9 Multichip Synchronization ............................................................ 48 Absolute Maximum Ratings .......................................................... 11 Normal Mode .............................................................................. 48 Thermal Characteristics ............................................................ 11 Timestamp Mode ....................................................................... 48 ESD Caution ................................................................................ 11 SYSREF Input ........................................................................... 50 Pin Configuration and Function Descriptions ........................... 12 SYSREF Setup/Hold Window Monitor ................................. 52 Typical Performance Characteristics ........................................... 14 Latency ............................................................................................. 54 AD9234-1000 .............................................................................. 14 End to End Total Latency .......................................................... 54 AD9234-500 ................................................................................ 18 Example Latency Calculation ................................................... 54 Equivalent Circuits ......................................................................... 22 Test Modes ....................................................................................... 55 Theory of Operation ...................................................................... 24 ADC Test Modes ........................................................................ 55 ADC Architecture ...................................................................... 24 JESD204B Block Test Modes .................................................... 56 Analog Input Considerations .................................................... 24 Serial Port Interface ........................................................................ 58 Voltage Reference ....................................................................... 27 Configuration Using the SPI ..................................................... 58 Clock Input Considerations ...................................................... 28 Hardware Interface ..................................................................... 58 Clock Jitter Considerations ....................................................... 29 SPI Accessible Features .............................................................. 58 Power-Down/Standby Mode..................................................... 29 Memory Map .................................................................................. 59 Temperature Diode .................................................................... 29 Reading the Memory Map Register Table ............................... 59 ADC Overrange and Fast Detect .................................................. 30 Memory Map Register Table ..................................................... 60 ADC Overrange .......................................................................... 30 Applications Information .............................................................. 71 Fast Threshold Detection (FD A and FD B) ........................ 30 Power Supply Recommendations ............................................. 71 Signal Monitor ................................................................................ 31 Exposed Pad Thermal Heat Slug Recommendations ............ 71 Digital Downconverter (DDC) ..................................................... 34 AVDD1 SR (Pin 57) and AGND (Pin 56 and Pin 60) .............. 71 DDC General Description ........................................................ 34 Outline Dimensions ....................................................................... 72 Half-Band Filter .......................................................................... 35 Ordering Guide .......................................................................... 72 DDC Gain Stage ......................................................................... 36 Rev. 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