Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Data Sheet AD9253 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD 1.8 V supply operation 14 Low power: 110 mW per channel at 125 MSPS with scalable D0+A SERIAL VIN+A DIGITAL LVDS D0A PIPELINE power options SERIALIZER VINA ADC D1+A SERIAL LVDS SNR = 74 dB (to Nyquist) 14 D1A VIN+B DIGITAL PIPELINE D0+B SERIAL SFDR = 90 dBc (to Nyquist) SERIALIZER VINB ADC LVDS D0B RBIAS DNL = 0.75 LSB (typical) INL = 2.0 LSB (typical) SERIAL D1+B VREF LVDS D1B Serial LVDS (ANSI-644, default) and low power, reduced SENSE FCO+ 1V signal option (similar to IEEE 1596.3) AD9253 REF FCO SELECT 650 MHz full power analog bandwidth D0+C SERIAL AGND 14 LVDS D0C 2 V p-p input voltage range VIN+C DIGITAL PIPELINE D1+C SERIAL SERIALIZER VINC ADC Serial port control LVDS D1C 14 D0+D SERIAL Full chip and individual channel power-down modes VIN+D LVDS DIGITAL D0D PIPELINE Flexible bit orientation SERIALIZER VIND ADC SERIAL D1+D LVDS D1D Built-in and custom digital test pattern generation SERIAL PORT DCO+ CLOCK Multichip sync and clock divider INTERFACE VCM MANAGEMENT DCO Programmable output clock and data alignment Programmable output resolution Standby mode APPLICATIONS Figure 1. Medical ultrasound High speed imaging as programmable output clock and data alignment and digital Quadrature radio receivers test pattern generation. The available digital test patterns Diversity radio receivers include built-in deterministic and pseudorandom patterns, along Test equipment with custom user-defined test patterns entered via the serial port GENERAL DESCRIPTION interface (SPI). The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS The AD9253 is available in a RoHS-compliant, 48-lead LFCSP. analog-to-digital converter (ADC) with an on-chip sample- It is specified over the industrial temperature range of 40C to and-hold circuit designed for low cost, low power, small size, +85C. This product is protected by a U.S. patent. and ease of use. The product operates at a conversion rate of PRODUCT HIGHLIGHTS up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small 1. Small Footprint. Four ADCs are contained in a small, space- package size is critical. saving package. 2. Low power of 110 mW/channel at 125 MSPS with scalable The ADC requires a single 1.8 V power supply and LVPECL-/ power options. CMOS-/LVDS-compatible sample rate clock for full performance 3. Pin compatible to the AD9633 12-bit quad ADC. operation. No external reference or driver components are 4. Ease of Use. A data clock output (DCO) operates at required for many applications. frequencies of up to 500 MHz and supports double data The ADC automatically multiplies the sample rate clock for the rate (DDR) operation. appropriate LVDS serial data rate. A data clock output (DCO) for 5. User Flexibility. The SPI control offers a wide range of capturing data on the output and a frame clock output (FCO) flexible features to meet specific system requirements. for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. CSB SDIO/OLM SCLK/DTP SYNC CLK+ CLK 10065-001AD9253 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 23 Applications ....................................................................................... 1 Power Dissipation and Power-Down Mode ........................... 25 General Description ......................................................................... 1 Digital Outputs and Timing ..................................................... 26 Functional Block Diagram .............................................................. 1 Output Test Modes ..................................................................... 29 Product Highlights ........................................................................... 1 Serial Port Interface (SPI) .............................................................. 30 Revision History ............................................................................... 2 Configuration Using the SPI ..................................................... 30 Specifications ..................................................................................... 3 Hardware Interface ..................................................................... 31 DC Specifications ......................................................................... 3 Configuration Without the SPI ................................................ 31 AC Specifications .......................................................................... 4 SPI Accessible Features .............................................................. 31 Digital Specifications ................................................................... 5 Memory Map .................................................................................. 32 Switching Specifications .............................................................. 6 Reading the Memory Map Register Table ............................... 32 Timing Specifications .................................................................. 6 Memory Map Register Table ..................................................... 33 Absolute Maximum Ratings .......................................................... 10 Memory Map Register Descriptions ........................................ 36 Thermal Resistance .................................................................... 10 Applications Information .............................................................. 38 ESD Caution ................................................................................ 10 Design Guidelines ...................................................................... 38 Pin Configuration and Function Descriptions ........................... 11 Power and Ground Recommendations ................................... 38 Typical Performance Characteristics ........................................... 13 Clock Stability Considerations ................................................. 38 AD9253-80 .................................................................................. 13 Exposed Pad Thermal Heat Slug Recommendations ............ 38 AD9253-105 ................................................................................ 15 VCM ............................................................................................. 38 AD9253-125 ................................................................................ 17 Reference Decoupling ................................................................ 38 Equivalent Circuits ......................................................................... 20 SPI Port ........................................................................................ 38 Theory of Operation ...................................................................... 21 Crosstalk Performance .............................................................. 39 Analog Input Considerations .................................................... 21 Outline Dimensions ....................................................................... 40 Voltage Reference ....................................................................... 22 Ordering Guide .......................................................................... 40 REVISION HISTORY 1/2018Rev. B to Rev. C Changes to Figure 3 ................................................................................ 7 Changes to Figure 3 .......................................................................... 7 Changes to Figure 5 ............................................................................ 8 Changes to Figure 5 .......................................................................... 8 Changes to Pin 9 to Pin 14 and Pin 23 to Pin 28 Descriptions .......11 Changes to Table 8 .......................................................................... 11 Changes to Figure 48 and Figure 49 ............................................ 20 Changes to Power Dissipation and Power-Down Mode Section .. 25 Changes to Clock Input Options Section .................................... 23 Updated Outline Dimensions ....................................................... 40 Changes to Jitter Considerations Section .................................... 25 Changes to Ordering Guide .......................................................... 40 Changes to Digital Outputs and Timing Section ....................... 26 Changes to Table 11 ....................................................................... 28 10/2015Rev. A to Rev. B Changes to Table 12 ....................................................................... 29 Added Note 4, Table 4 ...................................................................... 6 Changes to Channel-Specific Registers Section ......................... 32 Changes to Digital Outputs and Timing Section ....................... 27 Changes to Output Phase (Register 0x16) Section .................... 36 Changes to Clock Stability Considerations Section ................... 38 Changes to Resolution/Sample Rate Override (Register 0x100) Section .............................................................................................. 37 9/2014Rev. 0 to Rev. A Added Clock Stability Considerations Section........................... 38 Changes to Table 2 ............................................................................ 4 Updated Outline Dimensions ....................................................... 40 Added Propagation Delay Parameters of 1.5 ns (Min) and 3.1 ns (Max) Table 4, Changed t from 0.24 ns Typ to 10/2011Revision 0: Initial Version SSYNC 1.2 ns Min, and Changed tHSYNC from 0.40 ns Typ to 0.2 ns Min Table 5 ......................................................................... 6 Rev. C Page 2 of 40