14-Bit, 150 MSPS, 1.8 V Analog-to-Digital Converter AD9254 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD 1.8 V analog supply operation 1.8 V to 3.3 V output supply AD9254 SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input VIN+ 8-STAGE SHA MDAC1 A/D SFDR = 84 dBc to 70 MHz input 1 1/2-BIT PIPELINE VIN Low power: 430 mW 150 MSPS 4 8 3 A/D REFT Differential input with 650 MHz bandwidth REFB On-chip voltage reference and sample-and-hold amplifier CORRECTION LOGIC OR DNL = 0.4 LSB 15 Flexible analog input: 1 V p-p to 2 V p-p range OUTPUT BUFFERS DCO Offset binary, Gray code, or twos complement data format D13 (MSB) VREF Clock duty cycle stabilizer D0 (LSB) Data output clock SENSE SCLK/DFS CLOCK 0.5V MODE Serial port control DUTY CYCLE SDIO/DCS SELECT STABILIZER REF CSB Built-in selectable digital test pattern generation SELECT Programmable clock and data alignment AGND CLK+ CLK PDWN DRGND APPLICATIONS Figure 1. Ultrasound equipment IF sampling in communications receivers CDMA2000, WCDMA, TD-SCDMA, and WiMax Battery-powered instruments Hand-held scopemeters The digital output data is presented in offset binary, Gray code, or Low cost digital oscilloscopes twos complement formats. A data output clock (DCO) is Macro, micro, and pico cell infrastructure provided to ensure proper latch timing with receiving logic. GENERAL DESCRIPTION The AD9254 is available in a 48-lead LFCSP and is specified over The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS the industrial temperature range (40C to +85C). analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. PRODUCT HIGHLIGHTS The product uses a multistage differential pipeline architecture 1. The AD9254 operates from a single 1.8 V power supply with output error correction logic to provide 14-bit accuracy at 150 MSPS data rates and guarantees no missing codes over the and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of 2. The patented SHA input maintains excellent performance user-selectable input ranges and offsets, including single-ended for input frequencies up to 225 MHz. applications. It is suitable for multiplexed systems that switch 3. The clock DCS maintains overall ADC performance over a full-scale voltage levels in successive channels and for sampling wide range of clock pulse widths. single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available 4. A standard serial port interface supports various product ADCs, the AD9254 is suitable for applications in features and functions, such as data formatting (offset communications, imaging, and medical ultrasound. binary, twos complement, or Gray coding), enabling the A differential clock input controls all internal conversion cycles. clock DCS, power-down, and voltage reference mode. A duty cycle stabilizer (DCS) compensates for wide variations in 5. The AD9254 is pin-compatible with the AD9233, allowing the clock duty cycle while maintaining excellent overall ADC a simple migration from 12 bits to 14 bits. performance. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 06216-001AD9254 TABLE OF CONTENTS Features .............................................................................................. 1 Timing ......................................................................................... 20 Applications ...................................................................................... 1 Serial Port Interface (SPI) ............................................................. 21 General Description ......................................................................... 1 Configuration Using the SPI .................................................... 21 Functional Block Diagram .............................................................. 1 Hardware Interface .................................................................... 21 Product Highlights ........................................................................... 1 Configuration Without the SPI ................................................ 21 Revision History ............................................................................... 2 Memory Map .................................................................................. 22 Specifications .................................................................................... 3 Reading the Memory Map Register Table .............................. 22 DC Specifications ......................................................................... 3 Memory Map Register Table .................................................... 23 AC Specifications ......................................................................... 4 Layout Considerations ................................................................... 25 Digital Specifications ................................................................... 5 Power and Ground Recommendations .................................. 25 Switching Specifications .............................................................. 6 CML ............................................................................................. 25 Timing Diagram ........................................................................... 6 RBIAS ........................................................................................... 25 Absolute Maximum Ratings ........................................................... 7 Reference Decoupling................................................................ 25 Thermal Resistance ...................................................................... 7 Evaluation Board ............................................................................ 26 ESD Caution.................................................................................. 7 Power Supplies ........................................................................... 26 Pin Configuration and Function Descriptions ............................ 8 Input Signals ............................................................................... 26 Equivalent Circuits ........................................................................... 9 Output Signals ............................................................................ 26 Typical Performance Characteristics ........................................... 10 Default Operation and Jumper Selection Settings ................ 27 Theory of Operation ...................................................................... 14 Alternative Clock Configurations ............................................ 27 Analog Input Considerations ................................................... 14 Alternative Analog Input Drive Configuration ..................... 27 Differential Input Configurations ............................................ 15 Schematics ................................................................................... 29 Voltage Reference ....................................................................... 16 Evaluation Board Layout ........................................................... 34 Clock Input Considerations ...................................................... 17 Bill of Materials .......................................................................... 37 Jitter Considerations .................................................................. 19 Outline Dimensions ....................................................................... 40 Power Dissipation and Standby Mode .................................... 19 Ordering Guide .......................................................................... 40 Digital Outputs ........................................................................... 20 REVISION HISTORY 11/2020Rev. 0 to Rev. A Changed CP-48-3 to CP-48-5 ...................................... Throughout Changes to Figure 3 .......................................................................... 8 Updated Outline Dimensions ....................................................... 40 Changes to Ordering Guide .......................................................... 40 10/2006Revision 0: Initial Version Rev. A Page 2 of 40