16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC AD9261 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD SNR: 83 dB (85 dBFS) to 10 MHz input OR SFDR: 87 dBc to 10 MHz input VIN+ SAMPLE D15 Noise figure: 15 dB LOW-PASS - CMOS RATE DECIMATION MODULATOR BUFFER Input impedance: 1 k FILTER CONVERTER VIN D0 Power: 340 mW PLL LOCKED 1.8 V analog supply operation PHASE 1.8 V to 3.3 V output supply CLK+ LOCKED VREF AD9261 CLK LOOP Selectable bandwidth 2.5 MHz/5 MHz/10 MHz SERIAL DCO CFILT INTERFACE Output data rate: 30 MSPS to 160 MSPS Integrated decimation filters AGND SDIO SCLK CSB DGND Integrated sample rate converter Figure 1. On-chip PLL clock multiplier On-chip voltage reference Offset binary, Gray code, or twos complement data format Serial control interface (SPI) APPLICATIONS Data acquisition Automated test equipment Instrumentation Medical imaging GENERAL DESCRIPTION The AD9261 is a single 16-bit analog-to-digital converter The digital output data is presented in offset binary, Gray code, (ADC) based on a continuous time (CT) sigma-delta (-) or twos complement format. A data clock output (DCO) is architecture that achieves 87 dBc of dynamic range over a 10 MHz provided to ensure proper timing with the receiving logic. input bandwidth. The integrated features and characteristics The AD9261 operates on a 1.8 V analog supply and a 1.8 V unique to the continuous time - architecture significantly to 3.3 V digital supply, consuming 340 mW. The AD9261 is simplify its use and minimize the need for external components. available in a 48-lead LFCSP and is specified over the industrial The AD9261 has a resistive input impedance that relaxes the temperature range (40C to +85C). requirements of the driver amplifier. In addition, a 32 oversam- PRODUCT HIGHLIGHTS pled fifth-order continuous time loop filter significantly attenuates 1. Continuous time - architecture efficiently achieves high out-of-band signals and aliases, reducing the need for external dynamic range and wide bandwidth. filters at the input. 2. Passive input structure reduces or eliminates the require- An external clock input or the integrated integer-N PLL provides ments for a driver amplifier. the 640 MHz internal clock needed for the oversampled conti- 3. An oversampling ratio of 32 and high order loop filter nuous time - modulator. On-chip decimation filters and provide excellent alias rejection reducing or eliminating sample rate converters reduce the modulator data rate from the need for antialiasing filters. 640 MSPS to a user-defined output data rate from 30 MSPS to 4. An integrated decimation filter, sample rate converter, PLL 160 MSPS, enabling a more efficient and direct interface. clock multiplier, and voltage reference provide ease of use. 5. This part operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 07803-001AD9261 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics .............................................9 Applications ...................................................................................... 1 Equivalent Circuits ......................................................................... 13 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 14 General Description ......................................................................... 1 Analog Input Considerations ................................................... 14 Product Highlights ........................................................................... 1 Clock Input Considerations ..................................................... 16 Revision History ............................................................................... 2 Power Dissipation and Standby Mode .................................... 18 Specifications .................................................................................... 3 Digital Engine ............................................................................. 19 DC Specifications ......................................................................... 3 Digital Outputs ........................................................................... 21 AC Specifications ......................................................................... 4 Timing ......................................................................................... 21 Digital Decimation Filtering Characteristics ........................... 4 Serial Port Interface (SPI) ............................................................. 23 Digital Specifications ................................................................... 5 Configuration Using the SPI .................................................... 23 Switching Specifications .............................................................. 6 Hardware Interface .................................................................... 24 Absolute Maximum Ratings ........................................................... 7 Memory Map .................................................................................. 25 Thermal Resistance ...................................................................... 7 Memory Map Definitions ......................................................... 25 ESD Caution.................................................................................. 7 Outline Dimensions ....................................................................... 27 Pin Configuration and Function Descriptions ............................ 8 Ordering Guide .......................................................................... 27 REVISION HISTORY 9/2020Rev. 0 to Rev. A Changed CP-48-1 to CP-49-9 ...................................... Throughout Changes to Figure 3 .......................................................................... 8 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 4/2010Revision 0: Initial Version Rev. A Page 2 of 28