X-On Electronics has gained recognition as a prominent supplier of AD9262BCPZ Analog to Digital Converters - ADC across the USA, India, Europe, Australia, and various other global locations. AD9262BCPZ Analog to Digital Converters - ADC are a product manufactured by Analog Devices. We provide cost-effective solutions for Analog to Digital Converters - ADC, ensuring timely deliveries around the world.

AD9262BCPZ Analog Devices

AD9262BCPZ electronic component of Analog Devices
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Part No.AD9262BCPZ
Manufacturer: Analog Devices
Category: Analog to Digital Converters - ADC
Description: Analog to Digital Converters - ADC 16 Bit Dual 2.5MHz Bandwidth ADC
Datasheet: AD9262BCPZ Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
1: USD 84.2486 ea
Line Total: USD 84.25 
Availability - 0
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0
Ship by Fri. 29 Nov to Thu. 05 Dec
MOQ : 12
Multiples : 12
12 : USD 141.6458

0
Ship by Wed. 27 Nov to Fri. 29 Nov
MOQ : 1
Multiples : 1
1 : USD 84.2486
10 : USD 77.8026
25 : USD 75.7545
100 : USD 73.6173

   
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16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC AD9262 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD SNR: 83 dB (85 dBFS) to 10 MHz input ORA SFDR: 87 dBc to 10 MHz input VIN+A SAMPLE D15A LOW-PASS CT - DC CMOS DECIMATION RATE Noise figure: 15 dB MODULATOR CORRECT BUFFER FILTER CONVERTER VINA D0A Input impedance: 1 k GAIN Power: 600 mW QUADRATURE ADJ ERROR VREF ESTIMATE 1.8 V analog supply operation PHASE AD9262 ADJ CFILT 1.8 V to 3.3 V output supply DCO Selectable bandwidth VINB D15B LOW-PASS SAMPLE CT - DC CMOS DECIMATION RATE MODULATOR CORRECT 2.5 MHz/5 MHz/10 MHz real BUFFER FILTER CONVERTER VIN+B D0B 5 MHz/10 MHz/20 MHz complex CLK+ PHASE- SERIAL ORB LOCKED INTERFACE Output data rate: 30 MSPS to 160 MSPS CLK LOOP Integrated dc and quadrature correction AGND SDIO SCLK CSB DGND Integrated decimation filters Figure 1 Integrated sample rate converter The AD9262 incorporates an integrated dc correction and On-chip PLL clock multiplier quadrature estimation block that corrects for gain and phase On-chip voltage reference mismatch between the two channels. This functional block Offset binary, Gray code, or twos complement data format proves invaluable in complex signal processing applications Serial control interface (SPI) such as direct conversion receivers. APPLICATIONS The digital output data is presented in offset binary, Gray code, Baseband quadrature receivers: CDMA2000, W-CDMA, or twos complement format. A data clock output (DCO) is multicarrier GSM/EDGE, 802.16x, and LTE provided to ensure proper timing with the receiving logic. The Quadrature sampling instrumentation AD9262 has the added feature of interleaving Channel A and Medical equipment Channel B data onto one 16-bit bus, simplifying on-board routing. Radio detection and ranging (RADAR) The ADC is available in three different bandwidth options of GENERAL DESCRIPTION 2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW. The AD9262 is a dual channel, 16-bit analog-to-digital conver- The AD9262 is available in a 64-lead LFCSP and is specified ter (ADC) based on a continuous time (CT) sigma-delta (-) over the industrial temperature range (40C to +85C). architecture that achieves 87 dBc of dynamic range over a 10 MHz input bandwidth. The integrated features and characteris- PRODUCT HIGHLIGHTS tics unique to the continuous time - architecture significantly 1. Continuous time - architecture efficiently achieves high simplify its use and minimize the need for external components. dynamic range and wide bandwidth. The AD9262 has a resistive input impedance that relaxes the 2. Passive input structure reduces or eliminates the require- requirements of the driver amplifier. In addition, a 32 oversam- ments for a driver amplifier. pled fifth-order continuous time loop filter significantly attenuates 3. An oversampling ratio of 32 and high order loop filter out-of-band signals and aliases, reducing the need for external provide excellent alias rejection reducing or eliminating the filters at the input. need for antialiasing filters. 4. An integrated decimation filter, sample rate converter, PLL An external clock input or the integrated integer-N PLL provides clock multiplier, and voltage reference provide ease of use. the 640 MHz internal clock needed for the oversampled conti- 5. Integrated dc correction and quadrature error correction. nuous time - modulator. On-chip decimation filters and sample 6. Operates from a single 1.8 V analog power supply and rate converters reduce the modulator data rate from 640 MSPS to a 1.8 V to 3.3 V output supply. user-defined output data rate between 30 MSPS and 160 MSPS, enabling a more efficient and direct interface. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07772-001AD9262 TABLE OF CONTENTS Features .............................................................................................. 1 AD9262BCPZ-10 ....................................................................... 12 Applications ....................................................................................... 1 Equivalent Circuits ......................................................................... 15 General Description ......................................................................... 1 Theory of Operation ...................................................................... 16 Functional Block Diagram .............................................................. 1 Analog Input Considerations ................................................... 16 Product Highlights ........................................................................... 1 Clock Input Considerations ...................................................... 18 Revision History ............................................................................... 2 Power Dissipation and Standby Mode .................................... 20 Specif icat ions ..................................................................................... 3 Digital Engine ............................................................................. 21 DC Specifications ......................................................................... 3 DC and Quadrature Error Correction (QEC) ........................ 23 AC Specifications .......................................................................... 4 Digital Outputs ........................................................................... 24 Digital Decimation Filtering Characteristics ............................ 5 Timing ......................................................................................... 25 Digital Specifications ................................................................... 6 Serial Port Interface (SPI) .............................................................. 26 Switching Specifications .............................................................. 7 Configuration Using the SPI ..................................................... 26 Absolute Maximum Ratings ............................................................ 8 Hardware Interface ..................................................................... 27 Thermal Resistance ...................................................................... 8 Applications Information .............................................................. 28 ESD Caution .................................................................................. 8 Filtering Requirement ................................................................ 28 Pin Configuration and Function Descriptions ............................. 9 Memory Map .................................................................................. 30 Typical Performance Characteristics ........................................... 10 Memory Map Definitions ......................................................... 30 AD9262BCPZ ............................................................................. 10 Outline Dimensions ....................................................................... 32 AD9262B CP Z-5 .......................................................................... 11 Ordering Guide .......................................................................... 32 REVISION HISTORY 2/10Rev. 0 to Rev. A Changes to Figure 61 ...................................................................... 28 1/10Revision 0: Initial Version Rev. A Page 2 of 32

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