16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9265 FEATURES PRODUCT HIGHLIGHTS SNR = 79.0 dBFS at 70 MHz and 125 MSPS 1. On-chip dither option for improved SFDR performance SFDR = 93 dBc at 70 MHz and 125 MSPS with low power analog input. Low power: 373 mW at 125 MSPS 2. Proprietary differential input that maintains excellent SNR 1.8 V analog supply operation performance for input frequencies up to 300 MHz. 1.8 V CMOS or LVDS output supply 3. Operation from a single 1.8 V supply and a separate digital Integer 1-to-8 input clock divider output driver supply accommodating 1.8 V CMOS or IF sampling frequencies to 300 MHz LVDS outputs. 154.3 dBm/Hz small signal input noise with 200 input 4. Standard serial port interface (SPI) that supports various impedance at 70 MHz and 125 MSPS product features and functions, such as data formatting Optional on-chip dither (offset binary, twos complement, or gray coding), enabling Programmable internal ADC voltage reference the clock duty cycle stabilizer, DCS, power-down, test Integrated ADC sample-and-hold inputs modes, and voltage reference mode. Flexible analog input range: 1 V p-p to 2 V p-p 5. Pin compatibility with the AD9255, allowing a simple Differential analog inputs with 650 MHz bandwidth migration from 16 bits down to 14 bits. ADC clock duty cycle stabilizer Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONS Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment FUNCTIONAL BLOCK DIAGRAM SENSE RBIAS PDWN AGND AVDD (1.8V) LVDS LVDS RS REFERENCE VREF AD9265 VCM DRVDD (1.8V) VIN+ TRACK-AND-HOLD VIN OUTPUT ADC STAGING 16 16 16-BIT DITHER CMOS OR D15 TO D0 CORE LVDS (DDR) CLK+ CLOCK OR MANAGEMENT CLK SYNC SERIAL PORT DCO SVDD SCLK/ SDIO/ CSB DFS DCS Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20092020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 08502-001AD9265 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ...................................................................... 28 Applications ...................................................................................... 1 Clock Input Considerations ..................................................... 29 Product Highlights ........................................................................... 1 Power Dissipation and Standby Mode .................................... 31 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 32 Revision History ............................................................................... 2 Timing ......................................................................................... 32 General Description ......................................................................... 3 Built-In Self-Test (BIST) and Output Test ................................. 33 Specifications .................................................................................... 4 Built-In Self-Test (BIST) ........................................................... 33 ADC DC Specifications ............................................................... 4 Output Test Modes .................................................................... 33 ADC AC Specifications ................................................................. 5 Serial Port Interface (SPI) ............................................................. 34 Digital Specifications ................................................................... 6 Configuration Using the SPI .................................................... 34 Switching Specifications ................................................................ 8 Hardware Interface .................................................................... 34 Timing Specifications .................................................................. 9 Configuration Without the SPI ................................................ 35 Absolute Maximum Ratings ......................................................... 10 SPI Accessible Features ............................................................. 35 Thermal Characteristics ............................................................ 10 Memory Map .................................................................................. 36 ESD Caution................................................................................ 10 Reading the Memory Map Register Table .............................. 36 Pin Configurations and Function Descriptions ......................... 11 Memory Map Register Table .................................................... 37 Typical Performance Characteristics ........................................... 15 Memory Map Register Descriptions ....................................... 39 Equivalent Circuits ......................................................................... 23 Applications Information ............................................................. 40 Theory of Operation ...................................................................... 25 Design Guidelines ...................................................................... 40 ADC Architecture ...................................................................... 25 Outline Dimensions ....................................................................... 41 Analog Input Considerations ................................................... 25 Ordering Guide .......................................................................... 41 REVISION HISTORY 11/2020Rev. C to Rev. D 3/2013Rev. A to Rev. B Changed CP-48-8 to CP-48-9 ...................................... Throughout Changes to Table 17 ....................................................................... 37 Changes to Figure 4 ........................................................................ 11 Updated Outline Dimensions ...................................................... 41 Changes to Figure 5 ........................................................................ 13 1/2010Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 41 Changes to Ordering Guide .......................................................... 41 Changes to Worst Other (Harmonic or Spur) Parameter, Table 2 ................................................................................................. 5 8/2013Rev. B to Rev. C Changes to Figure 77 ..................................................................... 29 Changes to Data Clock Output (DCO) Section ......................... 32 Changes to Input Clock Divider Section .................................... 30 Changes to Ordering Guide .......................................................... 41 Changes to Table 17 ....................................................................... 37 Updated Outline Dimensions ...................................................... 41 10/2009Revision 0: Initial Version Rev. D Page 2 of 44