16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9269 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V to 3.3 V output supply SPI Integrated quadrature error correction (QEC) AD9269 ORA SNR PROGRAMMING DATA D15A 77.6 dBFS at 9.7 MHz input VIN+A ADC 71 dBFS at 200 MHz input VINA D0A SFDR DCOA 93 dBc at 9.7 MHz input VREF QUADRATURE 80 dBc at 200 MHz input SENSE ERROR DRVDD Low power CORRECTION REF VCM SELECT 44 mW per channel at 20 MSPS ORB RBIAS 100 mW per channel at 80 MSPS D15B VINB Differential input with 700 MHz bandwidth ADC On-chip voltage reference and sample-and-hold circuit VIN+B D0B 2 V p-p differential analog input DCOB DNL = 0.5/+1.1 LSB Serial port control options DIVIDE DUTY CYCLE MODE 1 TO 6 STABILIZER CONTROLS Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer (DCS) CLK+ CLK SYNC DCS PDWN DFS OEB Integer 1-to-6 input clock divider Figure 1. Data output multiplex option Built-in selectable digital test pattern generation PRODUCT HIGHLIGHTS Energy-saving power-down modes 1. The AD9269 operates from a single 1.8 V analog power Data clock output (DCO) with programmable clock and supply and features a separate digital output driver supply data alignment to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent APPLICATIONS performance for input frequencies up to 200 MHz and is Communications designed for low cost, low power, and ease of use. Diversity radio systems 3. An optional SPI selectable dc correction and quadrature Multimode digital receivers error correction (QEC) feature corrects for dc offset, gain, GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA and phase mismatches between the two channels. I/Q demodulation systems 4. A standard serial port interface (SPI) supports various Smart antenna systems product features and functions, such as data output format- Battery-powered instruments ting, internal clock divider, power-down, DCO/data timing Handheld scope meters and offset adjustments, and voltage reference modes. Portable medical imaging 5. The AD9269 is packaged in a 64-lead RoHS-compliant Ultrasound LFCSP that is pin compatible with the AD9268 16-bit Radar/LIDAR ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC the AD9231 12-bit ADC, the AD6659 12-bit baseband diversity receiver, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com MUX OPTION CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 08538-001AD9269 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 22 Applications ....................................................................................... 1 Power Dissipation and Standby Mode .................................... 24 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 25 Product Highlights ........................................................................... 1 Timing ......................................................................................... 25 Revision History ............................................................................... 2 Built-In Self-Test (BIST) and Output Test .................................. 26 General Description ......................................................................... 3 Built-In Self-Test (BIST) ............................................................ 26 Specif icat ions ..................................................................................... 4 Output Test Modes ..................................................................... 26 DC Specifications ......................................................................... 4 Channel/Chip Synchronization .................................................... 27 AC Specifications .......................................................................... 6 DC and Quadrature Error Correction (QEC) ............................ 28 Digital Specifications ................................................................... 7 Serial Port Interface (SPI) .............................................................. 29 Switching Specifications .............................................................. 8 Configuration Using the SPI ..................................................... 29 Timing Specifications .................................................................. 9 Hardware Interface ..................................................................... 29 Absolute Maximum Ratings .......................................................... 10 Configuration Without the SPI ................................................ 30 Thermal Characteristics ............................................................ 10 SPI Accessible Features .............................................................. 30 ESD Caution ................................................................................ 10 Memory Map .................................................................................. 31 Pin Configuration and Function Descriptions ........................... 11 Reading the Memory Map Register Table ............................... 31 Typical Performance Characteristics ........................................... 13 Open Locations .......................................................................... 31 AD9269-80 .................................................................................. 13 Default Values ............................................................................. 31 AD9269-65 .................................................................................. 15 Memory Map Register Table ..................................................... 32 AD9269-40 .................................................................................. 16 Memory Map Register Descriptions ........................................ 34 AD9269-20 .................................................................................. 17 Applications Information .............................................................. 36 Equivalent Circuits ......................................................................... 18 Design Guidelines ...................................................................... 36 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 37 ADC Architecture ...................................................................... 19 Ordering Guide .......................................................................... 37 Analog Input Considerations .................................................... 19 Voltage Reference ....................................................................... 21 REVISION HISTORY 8/2016Rev. 0 to Rev. A Changes to Figure 3 ................................................................................. 8 Updated Outline Dimensions ............................................................... 37 1/2010Revision 0: Initial Version Rev. A Page 2 of 40