Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator Data Sheet AD9278 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator The AD9278 is designed for low cost, low power, small size, Low power: 88 mW per channel, TGC mode, 40 MSPS and ease of use for medical ultrasound and automotive radar. It 32 mW per channel, CW mode contains eight channels of a variable gain amplifier (VGA) with 10 mm 10 mm, 144-ball CSP-BGA a low noise preamplifier (LNA), an antialiasing filter (AAF), an TGC channel input-referred noise: 1.3 nV/Hz, max gain analog-to-digital converter (ADC), and an I/Q demodulator Flexible power-down modes with programmable phase rotation. Fast recovery from low power standby mode: <2 s Each channel features a variable gain range of 45 dB, a fully Overload recovery: <10 ns differential signal path, an active input preamplifier termination, Low noise preamplifier (LNA) and a maximum gain of up to 51 dB. The channel is optimized Input-referred noise: 1.25 nV/Hz, gain = 21.3 dB for high dynamic performance and low power in applications Programmable gain: 15.6 dB/17.9 dB/21.3 dB where a small package size is critical. 0.1 dB compression: 1000 mV p-p/ The LNA has a single-ended-to-differential gain that is selectable 750 mV p-p/450 mV p-p through the SPI. Assuming a 15 MHz noise bandwidth (NBW) Dual-mode active input impedance matching and a 21.3 dB LNA gain, the LNA input SNR is roughly 88 dB. Bandwidth (BW): >50 MHz In CW Doppler mode, each LNA output drives an I/Q demod- Variable gain amplifier (VGA) ulator that has independently programmable phase rotation Attenuator range: 45 dB to 0 dB with 16 phase settings. Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB Linear-in-dB gain control Power-down of individual channels is supported to increase Antialiasing filter (AAF) battery life for portable applications. Standby mode allows quick Programmable second-order LPF from 8 MHz to 18 MHz power-up for power cycling. In CW Doppler operation, the Programmable HPF VGA, AAF, and ADC are powered down. The ADC contains Analog-to-digital converter (ADC) several features designed to maximize flexibility and minimize SNR: 70 dB, 12 bits up to 65 MSPS system cost, such as a programmable clock, data alignment, and Serial LVDS (ANSI-644, low power/reduced signal) programmable digital test pattern generation. The digital test CW mode I/Q demodulator patterns include built-in fixed patterns, built-in pseudo random Individual programmable phase rotation patterns, and custom user-defined test patterns entered via the Output dynamic range per channel: >158 dBc/Hz serial port interface. Output-referred SNR: 153 dBc/Hz, 1 kHz offset, 3 dBFS FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 PDWN STBY DRVDD LO-A TO LO-H I/Q 8 CHANNELS DEMODULATOR LOSW-A TO LOSW-H LI-A TO LI-H DOUTA+ TO DOUTH+ 12-BIT SERIAL LNA VGA ADC LVDS AAF LG-A TO LG-H DOUTA TO DOUTH FCO+ DATA SERIAL FCO LO RATE REFERENCE PORT DCO+ GENERATION MULTIPLIER INTERFACE DCO Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20102012 Analog Devices, Inc. All rights reserved. RESET 4LO+ 4LO GAIN+ GAIN CWI CWI+ CWQ CWQ+ VREF RBIAS GPO 0:3 CSB SCLK SDIO CLK+ CLK 09424-001AD9278 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Circuits ......................................................................... 17 General Description ......................................................................... 1 Ultrasound Theory of Operation ................................................. 19 Functional Block Diagram .............................................................. 1 Channel Overview .......................................................................... 20 Revision History ............................................................................... 2 TGC Operation ........................................................................... 20 Specifications ..................................................................................... 3 CW Doppler Operation ............................................................. 33 AC Specifications .......................................................................... 3 Serial Port Interface (SPI) .............................................................. 37 Digital Specifications ................................................................... 6 Hardware Interface ..................................................................... 37 Switching Specifications .............................................................. 7 Memory Map .................................................................................. 39 ADC Timing Diagrams ............................................................... 8 Reading the Memory Map Table .............................................. 39 Absolute Maximum Ratings ............................................................ 9 Reserved Locations .................................................................... 39 Thermal Impedance ..................................................................... 9 Default Values ............................................................................. 39 ESD Caution .................................................................................. 9 Logic Levels ................................................................................. 39 Pin Configuration and Function Descriptions ........................... 10 Outline Dimensions ....................................................................... 43 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 43 TGC Mode ................................................................................... 13 CW Doppler Mode ..................................................................... 16 REVISION HISTORY /12Rev. 0 to Rev. A Changes to SNR in Features Section .............................................. 1 Added Mode IV to Table 1 and Table 1 Conditions .................... 3 Added Mode IV Clock Rate Parameters and Changed tEH and tEL from 6.25 ns to 4.8 ns Table 3 ................................................................... 7 Changes to Active Impedance Matching Section ....................... 23 Added Table 9 .................................................................................. 24 Changes to Figure 56 and Figure 57 ............................................. 28 Changes to Digital Outputs and Timing Section ....................... 30 Changes to 0x01 Bits 7:0 Description, Changes to 0x02 Bits 5:4 Description and Default Value Table 19 ..................................... 40 Updated Outline Dimensions ....................................................... 43 10/10Revision 0: Initial Version Rev. A Page 2 of 44